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w wm8983 mobile multimedia codec with 1w speaker driver wolfson microelectronics plc to receive regular email updates, sign up at http://www.wolfsonmicro.com/enews/ product preview, august 2005, rev 1.1 copyright ? 2005 wolfson microelectronics plc description the wm8983 is a low power, high quality stereo codec designed for portable multimedia applications. highly flexible analogue mixing functions enable new application features, combining hi-fi quality audio with voice communication. the device integrates preamps for stereo differential mics, and includes drivers for speaker, headphone and differential or stereo line output. external component requirements are reduced as no separate microphone or headphone amplifiers are required. advanced on-chip digital signal processing includes a 5-band equaliser, a mixed signal automatic level control for the microphone or line input through the adc as well as a purely digital limiter function for record or playback. a programmable high pass filter in the adc path is provided for wind noise reduction and an iir with programmable coefficients can be used as a notch filter to suppress fixed-frequency noise. the wm8983 digital audio interface can operate in master or slave mode, while an integrated pll supports flexible clocking schemes. a-law and -law companding are fully supported. the wm8983 operates at analogue supply voltages from 2.5v to 3.3v, although the digital core can operate at voltages down to 1.71v to save power. speaker supplies can operate up to 5v for increased speaker output power. additional power management control enables individual sections of the chip to be powered down under software control. features stereo codec: ? dac snr 98db, thd -84db (a weighted @ 48khz) ? adc snr 95db, thd -84db (a weighted @ 48khz) ? speaker driver (1w into 8 ? btl with 5v supply) ? headphone driver with capless option ? 40mw per channel output power into 16 ? / 3.3v avdd2 ? pop and click suppression mic preamps: ? stereo differential or mono microphone interfaces ? programmable preamp gain ? psuedo differential inputs with common mode rejection ? programmable alc / noise gate in adc path ? low-noise bias supplied for electret microphones other features: ? enhanced 3-d function for improved stereo separation ? highly flexible mixing functions ? 5-band equaliser (adc or dac path) ? adc programmable high pass filter (wind noise reduction) ? adc programmable iir notch filter ? aux inputs for stereo analog input signals or beep ? pll supporting various clocks between 8mhz-50mhz ? sample rates supported (khz): 8, 11.025, 16, 12, 16, 22.05, 24, 32, 44.1, 48 ? 2.5v to 3.6v analogue supplies ? 1.71v to 3.6v digital supplies ? 2.5v to 5.5v speaker supplies ? 5x5mm 32-pin qfn package applications ? multimedia phone
wm8983 product preview w pp rev 1.1 august 2005 2 table of contents description .......................................................................................................1 features.............................................................................................................1 applications .....................................................................................................1 table of contents .........................................................................................2 pin configuration...........................................................................................3 ordering information ..................................................................................3 pin description ................................................................................................4 absolute maximum ratings.........................................................................5 recommended operating conditions .....................................................5 electrical characteristics ......................................................................6 terminology ............................................................................................................ 9 speaker output thd versus power ......................................................10 power consumption ....................................................................................11 typical scenarios................................................................................................ 11 audio paths overview .................................................................................12 signal timing requirements .....................................................................13 system clock timing ........................................................................................... 13 audio interface timing C master mode ........................................................ 13 audio interface timing C slave mode............................................................ 14 control interface timing C 3-wire mode .................................................... 15 control interface timing C 2-wire mode .................................................... 16 internal power on reset circuit ..........................................................17 device description .......................................................................................19 introduction ......................................................................................................... 19 input signal path ................................................................................................. 21 analogue to digital converter (adc).......................................................... 29 input limiter / automatic level control (alc) .......................................... 33 output signal path ............................................................................................. 38 3d stereo enhancement .................................................................................... 45 analogue outputs............................................................................................... 45 digital audio interfaces................................................................................... 62 audio sample rates ............................................................................................. 69 master clock and phase locked loop (pll) ............................................... 69 general purpose input/output...................................................................... 72 output switching (jack detect)..................................................................... 72 control interface.............................................................................................. 74 resetting the chip .............................................................................................. 75 power supplies .................................................................................................... 75 power management ............................................................................................ 75 register map...................................................................................................77 digital filter characteristics ...............................................................79 terminology .......................................................................................................... 79 dac filter responses......................................................................................... 80 adc filter responses......................................................................................... 80 highpass filter..................................................................................................... 81 5-band equaliser .................................................................................................. 82 applications information .........................................................................86 recommended external components .......................................................... 86 important notice ..........................................................................................88
product preview wm8983 w pp rev 1.1 august 2005 3 pin configuration ordering information order code temperature range package moisture sensitivity level peak soldering temperature wm8983gefl -25 c to +85 c 32-pin qfn (5 x 5 mm) (lead free) msl1 260 o c wm8983gefl/r -25 c to +85 c 32-pin qfn (5 x 5 mm) (lead free, tape and reel) msl1 260 o c note: reel quantity = 3,500
wm8983 product preview w pp rev 1.1 august 2005 4 pin description pin name type description 1 lip analogue input left mic pre-amp positive input 2 lin analogue input left mic pre-amp negative input 3 l2/gpio2 analogue input left channel line input/secondary mic pre-amp positive input/gpio2 pin 4 rip analogue input right mic pre-amp positive input 5 rin analogue input right mic pre-amp negative input 6 r2/gpio3 analogue input right channel line input/secondary mic pre-amp positive input/gpio3 pin 7 lrc digital input / output dac and adc sample rate clock 8 bclk digital input / output digital audio bit clock 9 adcdat digital output adc digital audio data output 10 dacdat digital input dac digital audio data input 11 mclk digital input master clock input 12 dgnd supply digital ground 13 dcvdd supply digital core logic supply 14 dbvdd supply digital buffer (i/o) supply 15 csb/gpio1 digital input / output 3-wire control interface chip select / gpio1 pin 16 sclk digital input 3-wire control interface clock input / 2-wire control interface clock input 17 sdin digital input / output 3-wire control interface data input / 2-wire control interface data input 18 mode digital input control interface selection 19 auxl analogue input left auxillary input 20 auxr analogue input right auxillary input 21 out4 analogue output right line output or mono mix output 22 out3 analogue output mono or left line output 23 rout2 analogue output headphone or line output right 2 24 agnd2 supply analogue ground (feeds rout2/lout2 and out3/out4) 25 lout2 analogue output headphone or line output left 2 26 avdd2 supply analogue supply (feeds output amplifiers rout2/lout2 and out3/out4) 27 vmid reference decoupling for adc and dac reference voltage 28 agnd1 supply analogue ground (feeds all input amplifiers, pll, adc and dac, internal bias circuits, output amplifiers lout1, rout1) 29 rout1 analogue output headphone or line output right 1 30 lout1 analogue output headphone or line output left 1 31 avdd1 supply analogue supply (feeds all input amplifiers, pll, adc and dac, internal bias circuits, output amplifiers lout1, lout2)) 32 micbias analogue output microphone bias note: it is recommended that the qfn ground paddle should be connected to analogue ground on the application pcb.
product preview wm8983 w pp rev 1.1 august 2005 5 absolute maximum ratings absolute maximum ratings are stress ratings only. permanent damage to the device may be caused by continuously operating at or beyond these limits. device functional operating limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified. esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. proper esd precautions must be taken during handling and storage of this device. wolfson tests its package types according to ipc/jedec j-std-020b for moisture sensitivity to determine acceptable storage conditions prior to surface mount assembly. these levels are: msl1 = unlimited floor life at <30 c / 85% relative humidity. not normally stored in moisture barrier bag. msl2 = out of bag storage for 1 year at <30 c / 60% relative humidity. supplied in moisture barrier bag. msl3 = out of bag storage for 168 hours at <30 c / 60% relative humidity. supplied in moisture barrier bag. the moisture sensitivity level for each package type is specified in ordering information. condition min max dbvdd, dcvdd, avdd1 supply voltages -0.3v +3.63v avdd2 supply voltage -0.3v +7v voltage range digital inputs dgnd -0.3v dvdd +0.3v voltage range analogue inputs agnd1 -0.3v avdd1 +0.3v storage temperature prior to soldering 30 c max / 85% rh max storage temperature after soldering -65 c +150 c notes 1. analogue and digital grounds must always be within 0.3v of each other. 2. all digital and analogue supplies are completely independent from each other. 3. analogue supply voltages should not be less than digital supply voltages. 4. in non-boosted mode avdd2 should be avdd1. in boost mode, avdd2 should be 1.5 x avdd1. recommended operating conditions parameter symbol test conditions min typ max unit digital supply range (core) dcvdd 1.71 1.8 3.6 v digital supply range (buffer) dbvdd 1.71 2 3.3 3.6 v analogue supply range avdd1 2.5 3.3 3.6 v speaker supply range avdd2 2.5 3.3 5.5 v ground dgnd, agnd1, agnd2 0 v notes 1. analogue supply voltages should not be less than digital supply voltages. 2. dbvdd should be 1.9v when using the pll.
wm8983 product preview w pp rev 1.1 august 2005 6 electrical characteristics test conditions dcvdd=1.8v, avdd1=avdd2=dbvdd=avdd2=3.3v, t a = +25 o c, 1khz signal, fs = 48khz, 24-bit audio data unless otherwise stated. parameter symbol test conditions min typ max unit microphone preamp inputs (lip, lin, rip, rin, l2, r2) full-scale input signal level C single ended input configuration via l/rin. note1 v infsse pgaboost = 0db inppgavol = 0db 1.0 0 vrms dbv full-scale input signal level C pseudo differential input configuration via l/rip and l/r2. note1 v infspd pgaboost = 0db inppgavol = 0db 0.707 -3 vrms dbv mic pga equivalent input noise at 35.25db gain 0 to 20khz 150 uv input resistance r micin gain set to 35.25db 1.6 k ? input resistance r micin gain set to 0db 47 k ? input resistance r micin gain set to -12db 75 k ? input resistance r micip rip2inppga = 1 90 k ? input resistance r micip rip2inppga = 0 90 k ? input capacitance c micin 10 pf mic programmable gain amplifier (pga) programmable gain -12 35.25 db programmable gain step size guaranteed monotonic 0.75 db mute attenuation 100 db selectable input gain boost (0/+20db) boost disabled 0 db gain boost on pga input boost enabled 20 db gain range from auxl/r or l/r2 input to boost/mixer -12 +6 db gain step size to boost/mixer 3 db auxilliary analogue inputs (auxl, auxr) full-scale input signal level (0db) C note this is proportional to avdd1 v infs avdd1/3.3 0 vrms dbv r auxinlmin left input boost and mixer enabled, at max gain 4.3 k ? r auxinltyp left input boost and mixer enabled, at 0db gain 8.6 k ? r auxinlmax left input boost and mixer enabled, at min gain 39.1 k ? r auxinrmin right input boost, mixer and beep enabled, at max gain 3 k ? r auxinrtyp right input boost, mixer and beep enabled, at 0db gain 6 k ? input resistance r auxinrmax right input boost, mixer and beep enabled, at min gain 29 k ? input capacitance c micin 10 pf automatic level control (alc) target record level -22.5 -1.5 db programmable gain -12 35.25
product preview wm8983 w pp rev 1.1 august 2005 7 test conditions dcvdd=1.8v, avdd1=avdd2=dbvdd=avdd2=3.3v, t a = +25 o c, 1khz signal, fs = 48khz, 24-bit audio data unless otherwise stated. parameter symbol test conditions min typ max unit gain hold time (note 2,4) t hold m clk = 12.288mhz (note 2) 0, 2.67, 5.33, 10.67, , 43691 (time doubles with each step) ms alcmode=0 (alc), mclk=12.288mhz (note 2) 3.3, 6.6, 13.1, , 3360 (time doubles with each step) gain ramp-up (decay) time (note 3,4) t dcy alcmode=1 (limiter), mclk=12.288mhz (note 2) 0.73, 1.45, 2.91, , 744 (time doubles with each step) ms alcmode=0 (alc), mclk=12.288mhz (note 2) 0.83, 1.66, 3.33, , 852 (time doubles with each step) gain ramp-down (attack) time (note 3,4) t atk alcmode=1 (limiter), mclk=12.288mhz (note 2) 0.18, 0.36, 0.73, , 186 (time doubles with each step) ms mute attenuation 80db db analogue to digital converter (adc) signal to noise ratio (note 5,6) a-weighted, 0db gain 95 db total harmonic distortion (note 7) full-scale, 0db gain -84 db channel separation (note 8) 1khz input signal 110 db digital to analogue converter (dac) to l/r mix to line-out (lout1, rout1 with 10k ? ? ? ? / 50pf load) full-scale output pga gains set to 0db avdd1/3.3 vrms signal to noise ratio (note 5,6) snr a-weighted 95 98 db signal to noise ratio (note 5,6) snr 22hz to 20khz 95.5 db total harmonic distortion (note 7) thd r l = 10k ? full-scale signal -84 db channel separation (note 8) 1khz signal 80 110 db output mixers (lmx1, rmx1) pga gain range into mixer -15 0 +6 db pga gain step into mixer 3 db analogue outputs (lout1, rout1, lout2, rout2) programmable gain range -57 0 +6 db programmable gain step size monotonic 1 db mute attenuation 1khz, full scale signal 85 db headphone output (aux to l/rmix to lout1, rout1. lout2, rout2 with 32 ? ? ? ? load) 0db full scale output voltage with > 32r load avdd1/3.3 vrms signal to noise ratio snr a-weighted 102 db r l = 16 ? , po=20mw avdd1=3.3v 0.003 -92 % db total harmonic distortion thd r l = 32 ? , po=20mw avdd1=3.3v 0.008 - 82 % db headphone output (dac to l/rmix to lout1, rout1 with 16 ? ? ? ? load) signal to noise ratio snr a-weighted 90 db signal to noise ratio snr 22hz to 20khz tbd db
wm8983 product preview w pp rev 1.1 august 2005 8 test conditions dcvdd=1.8v, avdd1=avdd2=dbvdd=avdd2=3.3v, t a = +25 o c, 1khz signal, fs = 48khz, 24-bit audio data unless otherwise stated. parameter symbol test conditions min typ max unit speaker output (lout2, rout2 with 8 ? ? ? ? bridge tied load, invrout2=1) spkboost=0 avdd2/ 3.3 full scale output voltage, 0db gain. (note 9) spkboost=1 (avdd2/ 3.3)*1.5 vrms output power p o output power is very closely correlated with thd; see below p o =200mw, r l = 8 ? , avdd2=3.3v 0.04 -68 % db p o =320mw, r l = 8 ? , avdd2=3.3v 1.0 -40 % db p o =500mw, r l = 8 ? , avdd2=5v 0.02 -74 % db total harmonic distortion thd p o =860mw, r l = 8 ? , avdd2=5v 1.0 -40 % db avdd2=3.3v, r l = 8 ? 90 db signal to noise ratio snr avdd2=5v, r l = 8 ? 90 db r l = 8 ? btl 80 db power supply rejection ratio (50hz-22khz) psrr r l = 8 ? btl avdd2=5v (boost) 69 db avdd2 = 5v other supplies disconnected tbd spkvdd leakage current avdd2 = 5v other supplies = 0v tbd ua out3/out4 outputs (with 10k ? ? ? ? / 50pf load) out3boost=0/ out4boost=0 avdd2/3.3 vrms full-scale output voltage, 0db gain (note 9) out3boost=1/ out4boost=1 1.5 x avdd2/3.3 vrms signal to noise ratio (note 5,6) snr a-weighted 98 db signal to noise ratio snr 22hz to 22khz 97.5 db total harmonic distortion (note 7) thd r l = 10 k ? full-scale signal -84 db channel separation (note 8) 1khz signal 80 100 db r l = 10k ? 52 db power supply rejection ratio (50hz-22khz) psrr r l = 10k ? , avdd2=5v 56 db microphone bias mbvsel=0 0.9*avdd1 v bias voltage v micbias mbvsel=1 0.65*avdd1 v bias current source i micbias for v micbias within +/-3% 3 ma output noise voltage vn 1khz to 20khz 15 nv/ hz digital input / output input high level v ih 0.7 dbv dd v input low level v il 0 .3 dbvdd v output high level v oh i ol =1ma 0.9 dbv dd v output low level v ol i oh -1ma 0 .1xdbvdd v input capacitance tbd pf input leakage tbd pa
product preview wm8983 w pp rev 1.1 august 2005 9 terminology 1. note the full scale input level is proportional to avdd1 and so will scale accordingly. 2. hold time is the length of time between a signal detected being too quiet and beginning to ramp up the gain. it does not apply to ramping down the gain when the signal is too loud, which happens without a delay. 3. ramp-up and ramp-down times are defined as the time it takes for the pga to sweep across 90% of its gain range. 4. all hold, ramp-up and ramp-down times scale proportionally with mclk 5. signal-to-noise ratio (db) C snr is a measure of the difference in level between the full scale output and the output with no signal applied. (no auto-zero or automute function is employed in achieving these results). 6. dynamic range (db) C dr is a measure of the difference between the highest and lowest portions of a signal. normally a thd+n measurement at 60db below full scale. the measured signal is then corrected by adding the 60db to it. (e.g. thd+n @ -60db= -32db, dr= 92db). 7. thd+n (db) C thd+n is a ratio, of the rms values, of (noise + distortion)/signal. 8. channel separation (db) C also known as cross-talk. this is a measure of the amount one channel is isolated from the other. normally measured by sending a full scale signal down one channel and measuring the other. 9. the maximum output voltage can be limited by the speaker power supply. if spkboost is set then avdd2 should be 1.5xavdd to prevent clipping taking place in the output stage (when pga gains are set to 0db).
wm8983 product preview w pp rev 1.1 august 2005 10 speaker output thd versus power figure 1 speaker thd+n vs output power (non-boost mode: spkvdd=3.3v; spkboost=0) figure 2 speaker thd+n vs output power (boost mode: spkvdd=5v; spkboost=1)
product preview wm8983 w pp rev 1.1 august 2005 11 power consumption typical scenarios estimated current consumption for typical scenarios are shown below. power delivered to the load is not included. mode i avdd1 ma (3.3v) i avdd2 ma (3.3v) i dcvdd ma (1.8v) i dbvdd ma (1.8v) total mw off (no clocks, temperature sensor disabled) 0.010 0.010 0.001 0.002 0.071 sleep (vref maintained) 0.100 0.001 0.012 0.003 0.360 mono record from differential mic (8khz, pll enabled) 4.000 0.001 0.400 0.030 13.97 stereo hp playback (44.1khz, pll enabled) 3.700 0.950 2.100 0.100 19.31 table 1 power consumption
wm8983 product preview w pp rev 1.1 august 2005 12 audio paths overview
product preview wm8983 w pp rev 1.1 august 2005 13 signal timing requirements system clock timing mclk t mclkl t mclkh t mclky figure 3 system clock timing requirements test conditions dcvdd=1.8v, dbvdd=avdd1=avdd2=3.3v, dgnd=agnd1=agnd2=0v, t a = +25 o c, slave mode parameter symbol conditions min typ max unit system clock timing information mclk=sysclk (=256fs) 81.38 ns mclk cycle time t mclky mclk input to pll note 1 20 ns mclk duty cycle t mclkds 60:40 40:60 note: 1. pll pre-scaling and pll n and k values should be set appropriately so that sysclk is no greater than 12.288mhz. audio interface timing C master mode figure 4 digital audio data timing C master mode (see control interface)
wm8983 product preview w pp rev 1.1 august 2005 14 test conditions dcvdd=1.8v, dbvdd=avdd1=avdd2=3.3v, dgnd=agnd1=agnd2=0v, t a =+25 o c, slave mode, fs=48khz, mclk=256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit audio data input timing information lrc propagation delay from bclk falling edge t dl 10 ns adcdat propagation delay from bclk falling edge t dda 10 ns dacdat setup time to bclk rising edge t dst 10 ns dacdat hold time from bclk rising edge t dht 10 ns audio interface timing C slave mode figure 5 digital audio data timing C slave mode test conditions dcvdd=1.8v, dbvdd=avdd1=avdd2=3.3v, dgnd=agnd1=agnd2=0v, t a =+25 o c, slave mode, fs=48khz, mclk= 256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit audio data input timing information bclk cycle time t bcy 50 ns bclk pulse width high t bch 20 ns bclk pulse width low t bcl 20 ns lrc set-up time to bclk rising edge t lrsu 10 ns lrc hold time from bclk rising edge t lrh 10 ns dacdat hold time from bclk rising edge t dh 10 ns adcdat propagation delay from bclk falling edge t dd 10 ns note: bclk period should always be greater than or equal to mclk period.
product preview wm8983 w pp rev 1.1 august 2005 15 control interface timing C 3-wire mode 3-wire mode is selected by connecting the mode pin high. figure 6 control interface timing C 3-wire serial control mode test conditions dcvdd=1.8v, dbvdd=avdd1=avdd2=3.3v, dgnd=agnd1=agnd2=0v, t a =+25 o c, slave mode, fs=48khz, mclk=256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit program register input information sclk rising edge to csb rising edge t scs 80 ns sclk pulse cycle time t scy 200 ns sclk pulse width low t scl 80 ns sclk pulse width high t sch 80 ns sdin to sclk set-up time t dsu 40 ns sclk to sdin hold time t dho 40 ns csb pulse width low t csl 40 ns csb pulse width high t csh 40 ns csb rising to sclk rising t css 40 ns pulse width of spikes that will be suppressed t ps 0 5 ns
wm8983 product preview w pp rev 1.1 august 2005 16 control interface timing C 2-wire mode 2-wire mode is selected by connecting the mode pin low. sdin sclk t 3 t 1 t 6 t 2 t 7 t 5 t 4 t 3 t 8 t 9 figure 7 control interface timing C 2-wire serial control mode test conditions dcvdd=1.8v, dbvdd=avdd1=avdd2=3.3v, dgnd=agnd1=agnd2=0v, t a =+25 o c, slave mode, fs=48khz, mclk=256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit program register input information sclk frequency 0 526 khz sclk low pulse-width t 1 1.3 us sclk high pulse-width t 2 600 ns hold time (start condition) t 3 600 ns setup time (start condition) t 4 600 ns data setup time t 5 100 ns sdin, sclk rise time t 6 300 ns sdin, sclk fall time t 7 300 ns setup time (stop condition) t 8 600 ns data hold time t 9 900 ns pulse width of spikes that will be suppressed t ps 0 5 ns
product preview wm8983 w pp rev 1.1 august 2005 17 internal power on reset circuit figure 8 internal power on reset circuit schematic the wm8983 includes an internal power-on-reset circuit, as shown in figure 8, which is used reset the digital logic into a default state after power up. the por circuit is powered from avdd1 and monitors dcvdd. it asserts porb low if avdd1 or dcvdd is below a minimum threshold. figure 9 typical power up sequence where avdd1 is powered before dcvdd figure 9 shows a typical power-up sequence where avdd1 comes up first. when avdd1 goes above the minimum threshold, v pora , there is enough voltage for the circuit to guarantee porb is asserted low and the chip is held in reset. in this condition, all writes to the control interface are ignored. now avdd1 is a t full s upply level. next dcvdd rises to v pord_on and porb is released high and all registers are in their default state and writes to the control interface may take place. on power down, where avdd1 falls first, porb is asserted low whenever avdd1 drops below the minimum threshold v pora_off .
wm8983 product preview w pp rev 1.1 august 2005 18 figure 10 typical power up sequence where dcvdd is powered before avdd1 figure 10 shows a typical power-up sequence where dcvdd comes up first. first it is assumed that dcvdd is already up to specified operating voltage. when avdd1 goes above the minimum threshold, v pora , there is enough voltage for the circuit to guarantee porb is asserted low and the chip is held in reset. in this condition, all writes to the control interface are ignored. when avdd1 rises to v pora_on , porb is released high and all registers are in their default state and writes to the control interface may take place. on power down, where dcvdd falls first, porb is asserted low whenever dcvdd drops below the minimum threshold v pord_off . symbol min typ max unit v pora 0.4 0.6 0.8 v v pora_on 0.9 1.2 1.6 v v pora_off 0.4 0.6 0.8 v v pord_on 0.5 0.7 0.9 v v pord_off 0.4 0.6 0.8 v table 2 typical por operation (typical values, not tested) notes: 1. if avdd1 and dcvdd suffer a brown-out (i.e. drop below the minimum recommended operating level but do not go below v pora_off or v pord_off ) then the chip will not reset and will resume normal operation when the voltage is back to the recommended level again. 2. the chip will enter reset at power down when avdd1 or dcvdd falls below v pora_off or v pord_off . this may be important if the supply is turned on and off frequently by a power management system. 3. the minimum t por period is maintained even if dcvdd and avdd1 have zero rise time. this specification is guaranteed by design rather than test.
product preview wm8983 w pp rev 1.1 august 2005 19 device description introduction the wm8983 is a low power audio codec combining a high quality stereo audio dac and adc, with flexible line and microphone input and output processing. features the chip offers great flexibility in use, and so can support many different modes of operation as follows: microphone inputs two pairs of stereo microphone inputs are provided, allowing a pair of stereo microphones to be pseudo-differentially connected, with user defined gain. the provision of the common mode input pin for each stereo input allows for rejection of common mode noise on the microphone inputs (level depends on gain setting chosen). a microphone bias is output from the chip which can be used to bias both microphones. the signal routing can be configured to allow manual adjustment of mic levels, or to allow the alc loop to control the level of mic signal that is transmitted. total gain through the microphone paths of up to +55.25db can be selected. pga and alc operation a programmable gain amplifier is provided in the input path to the adc. this may be used manually or in conjunction with a mixed analogue/digital automatic level control (alc) which keeps the recording volume constant. line inputs (auxl, auxr) auxl and auxr, can be used as a stereo line input or as an input for warning tones (or beeps) etc. these inputs can be summed into the record paths, along with the microphone preamp outputs, so allowing for mixing of audio with backing music etc as required. adc the stereo adc uses a 24-bit high-order oversampling architecture to deliver optimum performance with low power consumption. hi-fi dac the hi-fi dac provides high quality audio playback suitable for all portable audio hi-fi type applications, including mp3 players, portable multimedia devices and portable disc players of all types. output mixers flexible mixing is provided on the outputs of the device. a stereo mixer is provided for the stereo headphone or line outputs, lout1/rout1, and additional summers on the out3/out4 outputs allow for an optional differential or stereo line output on these pins. gain adjustment pgas are provided for the lout1/rout1 and lout2/rout2 outputs, and signal switching is provided to allow for all possible signal combinations.
wm8983 product preview w pp rev 1.1 august 2005 20 out3 and out4 can be configured to provide an additional stereo or mono differential lineout from the output of the dacs, the mixers or the input microphone boost stages. they can also provide a midrail reference for pseudo differential inputs to external amplifiers. audio interfaces the wm8983 has a standard audio interface, to support the transmission of stereo data to and from the chip. this interface is a 3 wire standard audio interface which supports a number of audio data formats including: ? i 2 s ? dsp/pcm mode (a burst mode in which lrc sync plus 2 data packed words are transmitted) ? msb-first, left justified ? msb-first, right justified the interface can operate in master or slave modes. control interfaces to allow full software control over all features, the wm8983 offers a choice of 2 or 3 wire control interface. it is fully compatible and an ideal partner for a wide range of industry standard microprocessors, controllers and dsps. selection of the mode is via the mode pin. in 2 wire mode, the address of the device is fixed as 0011010. clocking schemes wm8983 offers the normal audio dac clocking scheme operation, where 256fs mclk is provided to the dac and adc. a pll is included which may be used to generate these clocks in the event that they are not available from the system controller. this pll can accept a range of common input clock frequencies between 8mhz and 50mhz to generate high quality audio clocks. if this pll is not required for generation of these clocks, it can be reconfigured to generate alternative clocks which may then be output on the gpio pins and used elsewhere in the system. power control the design of the wm8983 has given much attention to power consumption without compromising performance. it operates at very low voltages, includes the ability to power off any unused parts of the circuitry under software control, and includes standby and power off modes. auxiliary analog input support additional stereo analog signals might be connected to the line inputs of wm8983 (e.g. melody chip or fm radio), and the stereo signal listened to via headphones, or recorded, simultaneously if required.
product preview wm8983 w pp rev 1.1 august 2005 21 input signal path the wm8983 has a number of flexible analogue inputs. there are two input channels, left and right, each of which consists of an input pga stage followed by a boost/mix stage which drives into the hi-fi adc. each input path has three input pins which can be configured in a variety of ways to accommodate single-ended, differential or dual differential microphones. there are two auxiliary input pins which can be fed into to the input boost/mix stage as well as driving into the output path. a bypass path exists from the output of the boost/mix stage into the output left/right mixers. microphone inputs the wm8983 can accommodate a variety of microphone configurations including single ended and pseudo differential inputs. the inputs to the left pseudo differential input pga are lip and l2. the inputs to the right pseudo differential input pga are rip and r2. lin and rin are used for a.c. coupled ground inputs. in single-ended microphone input configuration the microphone signal should be input to lin or rin and the non-inverting input of the input pga clamped to vmid. figure 11 microphone input pga circuit the input pgas are enabled by the ippgaenl/r register bits. register address bit label default description 2 inppgaenl 0 left channel input pga enable 0 = disabled 1 = enabled r2 power management 2 3 inppgaenr 0 right channel input pga enable 0 = disabled 1 = enabled table 3 input pga enable register settings
wm8983 product preview w pp rev 1.1 august 2005 22 register address bit label default description 0 lip2inppga 1 connect lip pin to left channel input pga amplifier positive terminal. 0 = lip not connected to input pga 1 = input pga amplifier positive terminal connected to lip (constant input impedance) 1 lin2inppga 1 connect lin pin to left channel input pga negative terminal. 0 = lin not connected to input pga 1 = lin connected to input pga amplifier negative terminal. 2 l2_2inppga 0 connect l2 pin to left channel input pga positive terminal. 0 = l2 not connected to input pga 1 = l2 connected to input pga amplifier positive terminal (constant input impedance). 4 rip2inppga 1 connect rip pin to right channel input pga amplifier positive terminal. 0 = rip not connected to input pga 1 = right channel input pga amplifier positive terminal connected to rip (constant input impedance) 5 rin2inppga 1 connect rin pin to right channel input pga negative terminal. 0 = rin not connected to input pga 1 = rin connected to right channel input pga amplifier negative terminal. r44 input control 6 r2_2inppga 0 connect r2 pin to right channel input pga positive terminal. 0 = r2 not connected to input pga 1 = r2 connected to input pga amplifier positive terminal (constant input impedance). table 4 input pga control input pga volume controls the input microphone pgas have a gain range from -12db to +35.25db in 0.75db steps. the gain from the lin/rin input to the pga output and from the l2/r2 amplifier to the pga output are always common and controlled by the register bits inppgavoll/r[5:0]. these register bits also affect the lip pin when lip2inppga=1, the l2 pin when l2_2inppga=1, the rip pin when rip2inppga=1 and the l2 pin when l2_2inppga=1. when the automatic level control (alc) is enabled the input pga gains are controlled automatically and the inppgavoll/r bits should not be used.
product preview wm8983 w pp rev 1.1 august 2005 23 register address bit label default description 5:0 inppgavoll 010000 left channel input pga volume 000000 = -12db 000001 = -11.25db . 010000 = 0db . 111111 = +35.25db 6 inppgamutel 0 mute control for left channel input pga: 0 = input pga not muted, normal operation 1 = input pga muted (and disconnected from the following input boost stage). 7 inppgazcl 0 left channel input pga zero cross enable: 0 = update gain when gain register changes 1 = update gain on 1 st zero cross after gain register write. r45 left channel input pga volume control 8 inppgavu not latched inppga left and inppga right volume do not update until a 1 is written to inppgavu (in reg 45 or 46) (see "volume updates" below) 5:0 inppgavolr 010000 right channel input pga volume 000000 = -12db 000001 = -11.25db . 010000 = 0db . 111111 = +35.25db 6 inppgamuter 0 mute control for right channel input pga: 0 = input pga not muted, normal operation 1 = input pga muted (and disconnected from the following input boost stage). 7 inppgazcr 0 right channel input pga zero cross enable: 0 = update gain when gain register changes 1 = update gain on 1 st zero cross after gain register write. r46 right channel input pga volume control 8 inppgavu not latched inppga left and inppga right volume do not update until a 1 is written to inppgavu (in reg 45 or 46) (see "volume updates" below) r32 alc control 1 8:7 alcsel 00 alc function select: 00 = alc off 01 = alc right only 10 = alc left only 11 = alc both on table 5 input pga volume control
wm8983 product preview w pp rev 1.1 august 2005 24 volume updates volume settings will not be applied to the pgas until a '1' is written to one of the inppgavu bits. this is to allow left and right channels to be updated at the same time, as shown in figure 12. figure 12 simultaneous left and right volume updates if the volume is adjusted while the signal is a non-zero value, an audible click can occur as shown in figure 13. figure 13 click noise during volume update in order to prevent this click noise, a zero cross function is provided. when enabled, this will cause the pga volume to update only when a zero crossing occurs, minimising click noise as shown in figure 14.
product preview wm8983 w pp rev 1.1 august 2005 25 figure 14 volume update using zero cross detection if there is a long period where no zero-crossing occurs, a timeout circuit in the wm8983 will automatically update the volume. the volume updates will occur between one and two timeout periods, depending on when the inppgavu bit is set as shown in figure 15. figure 15 volume update after timeout
wm8983 product preview w pp rev 1.1 august 2005 26 auxilliary inputs there are two auxiliary inputs, auxl and auxr which can be used for a variety of purposes such as stereo line inputs or as a beep input signal to be mixed with the outputs. as signal inputs, auxl/r inputs can be used as a line input to the input boost stage which has adjustable gain of -12db to +6db in 3db steps, with an additional "off" state (i.e. not connected to adc input). see the input boost section for further details. the auxl/r inputs can also be mixed into the output channel mixers, with a gain of -15db to +6db plus off. input boost each of the stereo input pga stages is followed by an input boost circuit. the input boost circuit has 3 selectable inputs: the input microphone pga output, the aux amplifier output and the l2/r2 input pin (can be used as a line input, bypassing the input pga). these three inputs can be mixed together and have individual gain boost/adjust as shown in figure 16. figure 16 input boost stage the input pga paths can have a +20db boost (pgaboostl/r=1) , a 0db pass through (pgaboostl/r=0) or be completely isolated from the input boost circuit (inppgamutel/r=1). register address bit label default description r47 left input boost control 8 pgaboostl 1 boost enable for left channel input pga: 0 = pga output has +0db gain through input boost stage. 1 = pga output has +20db gain through input boost stage. r48 right input boost control 8 pgaboostr 1 boost enable for right channel input pga: 0 = pga output has +0db gain through input boost stage. 1 = pga output has +20db gain through input boost stage. table 6 input boost stage control the auxilliary amplifier path to the boost stages is controlled by the auxl2boostvol[2:0] and auxr2boostvol[2:0] register bits. when auxl2boostvol/auxr2boostvol=000 this path is completely disconnected from the boost stage. settings 001 through to 111 control the gain in 3db steps from -12db to +6db. the l2/r2 path to the boost stage is controlled by the lip2boostvol[2:0] and the rip2boostvol[2:0] register bits. when l2_2boostvol/r2_2boostvol=000 the l2/r2 input pin is completely disconnected from the boost stage. settings 001 through to 111 control the gain in 3db steps from -12db to +6db.
product preview wm8983 w pp rev 1.1 august 2005 27 register address bit label default description 8:6 out4_2adcvol 000 controls the out4 to adc i nput boost stage: 000=path disabled (disconnected) 001=-12db gain through boost stage 010=-9db gain through boost stage 111=+6db gain through boost stage r42 out4 to adc 5 out4_2lnr 0 out4 to l or r adc i nput 0 = right adc input 1 = left adc input 2:0 auxl2boostvol 000 controls the auxiliary amplifier to the left channel input boost stage: 000=path disabled (disconnected) 001=-12db gain through boost stage 010=-9db gain through boost stage 111=+6db gain through boost stage r47 left channel input boost control 6:4 l2_2boostvol 000 controls the l2 pin to the left channel input boost stage: 000=path disabled (disconnected) 001=-12db gain through boost stage 010=-9db gain through boost stage 111=+6db gain through boost stage r48 right channel input boost control 2:0 auxr2boostvol 000 controls the auxiliary amplifier to the right channel input boost stage: 000=path disabled (disconnected) 001=-12db gain through boost stage 010=-9db gain through boost stage 111=+6db gain through boost stage 6:4 r2_2boostvol 000 controls the r2 pin to the right channel input boost stage: 000=path disabled (disconnected) 001=-12db gain through boost stage 010=-9db gain through boost stage 111=+6db gain through boost stage table 7 input boost stage control the boost stage is enabled under control of the boosten register bit.
wm8983 product preview w pp rev 1.1 august 2005 28 register address bit label default description 4 boostenl 0 left channel input boost enable 0 = boost stage off 1 = boost stage on r2 power management 2 5 boostenr 0 right channel input boost enable 0 = boost stage off 1 = boost stage on table 8 input boost enable control microphone biasing circuit the micbias output provides a low noise reference voltage suitable for biasing electret type microphones and the associated external resistor biasing network. refer to the applications information section for recommended external components. the micbias voltage can be altered via the mbvsel register bit. w hen mbvsel=0, micbias=0.9*avdd1 and when m bvsel=1, micbias=0.65*avdd1. the output can be enabled or disabled using the micben control bit. register address bit label default description r1 power management 1 4 micben 0 microphone bias enable 0 = off (high impedance output) 1 = on table 9 microphone bias enable control register address bit label default description r44 input control 8 mbvsel 0 microphone bias voltage control 0 = 0.9 * avdd1 1 = 0.65 * avdd1 table 10 microphone bias voltage control the internal micbias circuitry is shown in figure 17. note that the maximum source current capability for micbias is 3ma. the external biasing resistors therefore must be large enough to limit the micbias current to 3ma. figure 17 microphone bias schematic agnd1 mbvsel=0 micbias = 1.8 x vmid = 0.9 x avdd1 vmid internal resistor internal resistor micben mbvsel=1 micbias = 1.3 x vmid = 0.65 x avdd1 micbias
product preview wm8983 w pp rev 1.1 august 2005 29 analogue to digital converter (adc) the wm8983 uses stereo multi-bit, oversampled sigma-delta adcs. the use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. the adc full scale input level is proportional to avdd1. with a 3.3v supply voltage, the full scale level is 1.0v rms . any voltage greater than full scale may overload the adc and cause distortion. adc digital filters the adc filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data from the adc to the correct sampling frequency to be output on the digital audio interface. the digital filter path for each adc channel is illustrated in figure 18. figure 18 adc digital filter path the adcs are enabled by the adcenl/r register bit. register address bit label default description 0 adcenl 0 enable adc left channel: 0 = adc disabled 1 = adc enabled r2 power management 2 1 adcenr 0 enable adc right channel: 0 = adc disabled 1 = adc enabled table 11 adc enable control the polarity of the output signal can also be changed under software control using the adclpol/adcrpol register bit. the oversampling rate of the adc can be adjusted using the adcosr register bit. with adcosr=0 the oversample rate is 64x which gives lowest power operation and when adcosr=1 the oversample rate is 128x which gives best performance. register address bit label default description 0 adclpol 0 adc left channel polarity adjust: 0 = normal 1 = inverted 1 adcrpol 0 adc right channel polarity adjust: 0 = normal 1 = inverted r14 adc control 3 adcosr 0 adc oversample rate select: 0 = 64x (lower power) 1 = 128x (best performance) table 12 adc control
wm8983 product preview w pp rev 1.1 august 2005 30 selectable high pass filter a selectable high pass filter is provided. to disable this filter set hpfen=0. the filter has two modes controlled by hpfapp. in audio mode (hpfapp=0) the filter is first order, with a cut-off frequency of 3.7hz. in application mode (hpfapp=1) the filter is second order, with a cut-off frequency selectable via the hpfcut register. the cut-off frequencies when hpf app=1 are shown in table 14. register address bit label default description 8 hpfen 1 high pass filter enable 0 = disabled 1 = enabled 7 hpfapp 0 select audio mode or application mode 0 = audio mode (1 st order, fc = ~3.7hz) 1 = application mode (2 nd order, fc = hpfcut) r14 adc control 6:4 hpfcut 000 application mode cut-off frequency see table 14 for details. table 13 adc enable control sr=101/100 sr=011/010 sr=001/000 fs (khz) hpfcut [2:0] 8 11.025 12 16 22.05 24 32 44.1 48 000 82 113 122 82 113 122 82 113 122 001 102 141 153 102 141 153 102 141 153 010 131 180 156 131 180 156 131 180 156 011 163 225 245 163 225 245 163 225 245 100 204 281 306 204 281 306 204 281 306 101 261 360 392 261 360 392 261 360 392 110 327 450 490 327 450 490 327 450 490 111 408 563 612 408 563 612 408 563 612 table 14 high pass filter cut-off frequencies (hpfapp=1) note that the high pass filter values (when hpfapp=1) are calculated on the assumption that the sr register bits are set correctly for the actual sample rate as shown in table 14.
product preview wm8983 w pp rev 1.1 august 2005 31 programmable iir notch filter a programmable notch filter is provided. this filter has a variable centre frequency and bandwidth, programmable via two coefficients, a0 and a1. a0 and a1 are represented by the register bits nfa0[13:0] and nfa1[13:0]. because these coefficient values require four register writes to setup there is an nfu (notch filter update) flag which should be set only when all four registers are setup. register address bit label default description 6:0 nfa0[13:7] 0 notch filter a0 coefficient, bits [13:7] 7 nfen 0 notch filter enable: 0 = disabled 1 = enabled r27 notch filter 1 8 nfu 0 notch filter update. the notch filter values used internally only update when one of the nfu bits is set high. 6:0 nfa0[6:0] 0 notch filter a0 coefficient, bits [6:0] r28 notch filter 2 8 nfu 0 notch filter update. the notch filter values used internally only update when one of the nfu bits is set high. 6:0 nfa1[13:7] 0 notch filter a1 coefficient, bits [13:7] r29 notch filter 3 8 nfu 0 notch filter update. the notch filter values used internally only update when one of the nfu bits is set high. 0-6 nfa1[6:0] 0 notch filter a1 coefficient, bits [6:0] r30 notch filter 4 8 nfu 0 notch filter update. the notch filter values used internally only update when one of the nfu bits is set high. table 15 notch filter function the coefficients are calculated as follows: ) 2 / tan( 1 ) 2 / tan( 1 0 b b w w a + ? = ) cos( ) 1 ( 0 0 1 w a a + ? = where: s c f f w / 2 0 = s b b f f w / 2 = f c = centre frequency in hz, f b = -3db bandwidth in hz, f s = sample frequency in hz the actual register values can be determined from the coefficients as follows: nfa0 = -a0 x 2 13 nfa1 = -a1 x 2 12 digital adc volume control the output of the adcs can be digitally attenuated over a range from C127db to 0db in 0.5db steps. the gain for a given eight-bit code x is given by: 0.5 (g-255) db for 1 g 255; mute for g = 0
wm8983 product preview w pp rev 1.1 august 2005 32 register address bit label default description 7:0 adclvol [7:0] 11111111 ( 0db ) left adc digital volume control 0000 0000 = digital mute 0000 0001 = -127db 0000 0010 = -126.5db ... 0.5db steps up to 1111 1111 = 0db r15 left channel adc digital volume 8 adcvu not latched adc left and adc right volume do not update until a 1 is written to adcvu (in reg 15 or 16) 7:0 adcrvol [7:0] 11111111 ( 0db ) right adc digital volume control 0000 0000 = digital mute 0000 0001 = -127db 0000 0010 = -126.5db ... 0.5db steps up to 1111 1111 = 0db r16 right channel adc digital volume 8 adcvu not latched adc left and adc right volume do not update until a 1 is written to adcvu (in reg 15 or 16) table 16 adc digital volume control
product preview wm8983 w pp rev 1.1 august 2005 33 input limiter / automatic level control (alc) the wm8983 has an automatic pga gain control circuit, which can function as an input peak limiter or as an automatic level control (alc). in input peak limiter mode (alcmode bit = 1), a digital peak detector detects when the input signal goes above a predefined level and will ramp the pga gain down to prevent the signal becoming too large for the input range of the adc. when the signal returns to a level below the threshold, the pga gain is slowly returned to its starting level. the peak limiter cannot increase the pga gain above its static level. figure 19 input peak limiter operation in alc mode (alcmode bit = 0) the circuit aims to keep a constant recording volume irrespective of the input signal level. this is achieved by continuously adjusting the pga gain so that the signal level at the adc input remains constant. a digital peak detector monitors the adc output and changes the pga gain if necessary.
wm8983 product preview w pp rev 1.1 august 2005 34 figure 20 alc operation the alc/limiter function is enabled by setting the register bit alcsel. when enabled, the recording volume can be programmed between C6db and C28.5db (relative to adc full scale) using the alclvl register bits. an upper limit for the pga gain can be imposed by setting the alcmax control bits and a lower limit for the pga gain can be imposed by setting the alcmin control bits. alchld, alcdcy and alcatk control the hold, decay and attack times, respectively: hold time is the time delay between the peak level detected being below target and the pga gain beginning to ramp up. it can be programmed in power-of-two (2 n ) steps, e.g. 2.67ms, 5.33ms, 10.67ms etc. up to 43.7s. alternatively, the hold time can also be set to zero. the hold time is not active in limiter mode (alcmode = 1). the hold time only applies to gain ramp-up, there is no delay before ramping the gain down when the signal level is above target. decay (gain ramp-up) time is the time that it takes for the pga gain to ramp up and is given as a time per gain step, time per 6db change and time to ramp up over 90% of its range. the decay time can be programmed in power-of-two (2 n ) steps, from 3.3ms/6db, 6.6ms/6db, 13.1ms/6db, etc. to 3.36s/6db. attack (gain ramp-down) time is the time that it takes for the pga gain to ramp down and is given as a time per gain step, time per 6db change and time to ramp down over 90% of its range. the attack time can be programmed in power-of-two (2 n ) steps, from 832us/6db, 1.66ms/6db, 3.328us/6db, etc. to 852ms/6db. nb, in peak limiter mode the gain control circuit runs approximately 4x faster to allow reduction of fast peaks. attack and decay times for peak limiter mode are given below. the hold, decay and attack times given in table 17 are constant across sample rates so long as the sr bits are set correctly. e.g. when sampling at 48khz the sample rates stated in table 17 will only be correct if the sr bits are set to 000 (48khz). i f the actual sample rate was only 44.1khz then the hold, decay and attack times would be scaled down by 44.1/48. note: zero cross function can affect these time constants, and is not recommended for use during alc operation.
product preview wm8983 w pp rev 1.1 august 2005 35 register address bit label default description 8:7 alcsel 00 alc function select 00 = alc disabled 01 = right channel alc enabled 10 = left channel alc enabled 11 = both channels alc enabled 5:3 alcmaxgain [2:0] 111 (+35.25db) set maximum gain of pga 111 = +35.25db 110 = +29.25db 101 = +23.25db 100 = +17.25db 011 = +11.25db 010 = +5.25db 001 = -0.75db 000 = -6.75db r32 alc control 1 2:0 alcmingain [2:0] 000 (-12db) set minimum gain of pga 000 = -12db 001 = -6db 010 = 0db 011 = +6db 100 = +12db 101 = +18db 110 = +24db 111 = +30db 7:4 alchld [3:0] 0000 (0ms) alc hold time before gain is increased. 0000 = 0ms 0001 = 2.67ms 0010 = 5.33ms (time doubles with every step) 1111 = 43.691s 3:0 alclvl [3:0] 1011 (-12db) alc target C sets signal level at adc input 1111 = -1.5dbfs 1110 = -1.5dbfs 1101 = -3dbfs 1100 = -4.5dbfs ...... (-1.5db steps) 0001 = -21dbfs 0000 = -22.5dbfs r33 alc control 2 8 alczc 0 (zero cross off) alc uses zero cross detection circuit. (not recommended for use with alc)
wm8983 product preview w pp rev 1.1 august 2005 36 8 alcmode 0 determines the alc mode of operation: 0 = alc mode 1 = limiter mode. decay (gain ramp-up) time (alcmode ==0) per step per 6db 90% of range 0000 410us 3.3ms 24ms 0001 820us 6.6ms 48ms 0010 1.64ms 13.1ms 192ms (time doubles with every step) 0011 (13ms/6db) 1010 or higher 420ms 3.36s 24.576s decay (gain ramp-up) time (alcmode ==1) per step per 6db 90% of range 0000 90.8us 726.4us 5.26ms 0001 181.6us 1.453 ms 10.53 ms 0010 363.2us 2.905 ms 21.06 ms (time doubles with every step) 7:4 alcdcy [3:0] 0011 (2.9ms/6db) 1010 93ms 744ms 5.39s alc attack (gain ramp-down) time (alcmode == 0) per step per 6db 90% of range 0000 104us 832us 6ms 0001 208us 1.664 ms 12ms 0010 416us 3.328 ms 24.1ms (time doubles with every step) 0010 (832us/6db) 1010 or higher 106ms 852ms 6.18s alc attack (gain ramp-down) time (alcmode == 1) per step per 6db 90% of range 0000 22.7us 182.4us 1.31ms 0001 45.4us 363.2us 2.62ms 0010 90.8us 726.4us 5.26ms (time doubles with every step) r34 alc control 3 3:0 alcatk [3:0] 0010 (182us/6db) 1010 23.2ms 186ms 1.348s table 17 alc control registers when the alc is disabled, the input pga remains at the last controlled value of the alc. an input gain update must be made by writing to the inppgavoll/r register bits.
product preview wm8983 w pp rev 1.1 august 2005 37 minimum and maximum gain the alcmingain and alcmaxgain register sets the minimum/maximum gain value that the pga can be set to whilst under the control of the alc. this has no effect on the pga when alc is not enabled. peak limiter to prevent clipping when a large signal occurs just after a period of quiet, the alc circuit includes a limiter function. if the adc input signal exceeds 87.5% of full scale (C1.16db), the pga gain is ramped down at the maximum attack rate (as when alcatk = 0000), until the signal level falls below 87.5% of full scale. this function is automatically enabled whenever the alc is enabled. note: if alcatk = 0000, then the limiter makes no difference to the operation of the alc. it is designed to prevent clipping when long attack times are used. noise gate when the signal is very quiet and consists mainly of noise, the alc function may cause noise pumping, i.e. loud hissing noise during silence periods. the wm8983 has a noise gate function that prevents noise pumping by comparing the signal level at the input pins against a noise gate threshold, ngth. the noise gate cuts in when: signal level at adc [dbfs] < ngth [dbfs] + pga gain [db] + mic boost gain [db] this is equivalent to: signal level at input pin [dbfs] < ngth [dbfs] the pga gain is then held constant (preventing it from ramping up as it normally would when the signal is quiet). the table below summarises the noise gate control register. the ngth control bits set the noise gate threshold with respect to the adc full-scale range. the threshold is adjusted in 6db steps. levels at the extremes of the range may cause inappropriate operation, so care should be taken with setCup of the function. the noise gate only operates in conjunction with the alc and cannot be used in limiter mode. register address bit label default description 2:0 ngth 000 noise gate threshold: 000 = -39db 001 = -45db 010 = -51db (6db steps) 111 = -81db r35 alc noise gate control 3 ngaten 0 noise gate function enable 1 = enable 0 = disable table 18 alc noise gate control
wm8983 product preview w pp rev 1.1 august 2005 38 output signal path the wm8983 output signal paths consist of digital application filters, up-sampling filters, stereo hi-fi dacs, analogue mixers, stereo headphone and stereo line/mono/midrail output drivers. the digital filters and dac are enabled by register bits dacenl and dacenr. the mixers and output drivers can be separately enabled by individual control bits (see analogue outputs). thus it is possible to utilise the analogue mixing and amplification provided by the wm8983, irrespective of whether the dacs are running or not. the wm8983 dacs receive digital input data on the dacdat pin. the digital filter block processes the data to provide the following functions: ? digital volume control ? graphic equaliser ? a digital peak limiter. ? sigma-delta modulation high performance sigma-delta audio dac converts the digital data into an analogue signal. figure 21 dac digital filter path the analogue outputs from the dacs can then be mixed with the aux analogue inputs and the adc analogue inputs. the mix is fed to the output drivers for headphone (lout1/rout1, lout2/rout2) or line (out3/out4). out3 and out4 have additional mixers which allow them to output different signals to the headphone and line outputs. digital playback (dac) path digital data is passed to the wm8983 via the flexible audio interface and is then passed through a variety of advanced digital filters as shown in figure 21 to the hi-fi dacs. the dacs are enabled by the dacenl/r register bits. register address bit label default description 0 dacenl 0 left channel dac enable 0 = dac disabled 1 = dac enabled r3 power management 3 1 dacenr 0 right channel dac enable 0 = dac disabled 1 = dac enabled table 19 dac enable control the wm8983 also has a soft mute function, which when enabled, gradually attenuates the volume of the digital signal to zero. when disabled, the gain will ramp back up to the digital gain setting. this function is enabled by default. to play back an audio signal, it must first be disabled by setting the softmute bit to zero.
product preview wm8983 w pp rev 1.1 august 2005 39 register address bit label default description 0 dacpol 0 left dac output polarity: 0 = non-inverted 1 = inverted (180 degrees phase shift) 1 dacrpol 0 right dac output polarity: 0 = non-inverted 1 = inverted (180 degrees phase shift) 2 amute 0 automute enable 0 = amute disabled 1 = amute enabled 3 dacosr 0 dac oversampling rate: 0 = 64x (lowest power) 1 = 128x (best performance) r10 dac control 6 softmute 0 softmute enable: 0 = enabled 1 = disabled table 20 dac control register the digital audio data is converted to oversampled bit streams in the on-chip, true 24-bit digital interpolation filters. the bitstream data enters the multi-bit, sigma-delta dacs, which convert it to a high quality analogue audio signal. the multi-bit dac architecture reduces high frequency noise and sensitivity to clock jitter. it also uses a dynamic element matching technique for high linearity and low distortion. the dac output phase defaults to non-inverted. setting daclpol will invert the dac output phase on the left channel and dacrpol inverts the phase on the right channel. auto-mute the dac has an auto-mute function which applies an analogue mute when 1024 consecutive zeros are detected. the mute is released as soon as a non-zero sample is detected. auto-mute can be disabled using the amute control bit. digital hi-fi dac volume (gain) control the signal volume from each hi-fi dac can be controlled digitally. the gain range is C127db to 0db in 0.5db steps. the level of attenuation for an eight-bit code x is given by: 0.5 (x-255) db for 1 x 255; mute for x = 0
wm8983 product preview w pp rev 1.1 august 2005 40 register address bit label default description 7:0 daclvol [7:0] 11111111 ( 0db ) left dac digital volume control 0000 0000 = digital mute 0000 0001 = -127db 0000 0010 = -126.5db ... 0.5db steps up to 1111 1111 = 0db r11 left dac digital volume 8 dacvu not latched dac left and dac right volume do not update until a 1 is written to dacvu (in reg 11 or 12) 7:0 dacrvol [7:0] 11111111 ( 0db ) right dac digital volume control 0000 0000 = digital mute 0000 0001 = -127db 0000 0010 = -126.5db ... 0.5db steps up to 1111 1111 = 0db r12 right dac digital volume 8 dacvu not latched dac left and dac right volume do not update until a 1 is written to dacvu (in reg 11 or 12) table 21 dac digital volume control note: an additional gain of up to 12db can be added using the gain block embedded in the digital peak limiter circuit (see dac output limiter section). 5-band equaliser a 5-band graphic equaliser function which can be used to change the output frequency levels to suit the environment. this can be applied to the adc or dac path and is described in the 5-band equaliser section for further details on this feature. 3-d enhancement the wm8983 has an advanced digital 3-d enhancement feature which can be used to vary the perceived stereo separation o f the left and right channels. like the 5-band equaliser this feature can be applied to either the adc record path or the dac plaback path but not both simultaneously. refer to the 3-d stereo enhancement section for further details on this feature. dac digital output limiter the wm8983 has a digital output limiter function. the operation of this is shown in figure 22. in this diagram the upper graph shows the envelope of the input/output signals and the lower graph shows the gain characteristic.
product preview wm8983 w pp rev 1.1 august 2005 41 figure 22 dac digital limiter operation the limiter has a programmable upper threshold which is close to 0db. referring to figure 22, in normal operation (limboost=000 => limit only) signals below this threshold are unaffected by the limiter. signals above the upper threshold are attenuated at a specific attack rate (set by the limatk register bits) until the signal falls below the threshold. the limiter also has a lower threshold 1db below the upper threshold. when the signal falls below the lower threshold the signal is amplified at a specific decay rate (controlled by limdcy register bits) until a gain of 0db is reached. both threshold levels are controlled by the limlvl register bits. the upper threshold is 0.5db above the value programmed by limlvl and the lower threshold is 0.5db below the limlvl value. volume boost the limiter has programmable upper gain which boosts signals below the threshold to compress the dynamic range of the signal and increase its perceived loudness. this operates as an alc function with limited boost capability. the volume boost is from 0db to +12db in 1db steps, controlled by the limboost register bits. the output limiter volume boost can also be used as a stand alone digital gain boost when the limiter is disabled.
wm8983 product preview w pp rev 1.1 august 2005 42 register address bit label default description 3:0 limatk 0010 limiter attack time (per 6db gain change) for 44.1khz sampling. note that these are proportionally related to sample rate. 0000 = 94us 0001 = 188s 0010 = 375us 0011 = 750us 0100 = 1.5ms 0101 = 3ms 0110 = 6ms 0111 = 12ms 1000 = 24ms 1001 = 48ms 1010 = 96ms 1011 to 1111 = 192ms 7:4 limdcy 0011 limiter decay time (per 6db gain change) for 44.1khz sampling. note that these are proportionally related to sample rate: 0000 = 750us 0001 = 1.5ms 0010 = 3ms 0011 = 6ms 0100 = 12ms 0101 = 24ms 0110 = 48ms 0111 = 96ms 1000 = 192ms 1001 = 384ms 1010 = 768ms 1011 to 1111 = 1.536s r24 dac digital limiter control 1 8 limen 0 enable the dac digital limiter: 0 = disabled 1 = enabled 3:0 limboost 0000 limiter volume boost (can be used as a stand alone volume boost when limen=0): 0000 = 0db 0001 = +1db 0010 = +2db 0011 = +3db 0100 = +4db 0101 = +5db 0110 = +6db 0111 = +7db 1000 = +8db 1001 = +9db 1010 = +10db 1011 = +11db 1100 = +12db 1101 to 1111 = reserved r25 dac digital limiter control 2 6:4 limlvl 000 programmable signal threshold level (determines level at which the limiter starts to operate) 000 = -1db 001 = -2db 010 = -3db 011 = -4db 100 = -5db 101 to 111 = -6db table 22 dac digital limiter control
product preview wm8983 w pp rev 1.1 august 2005 43 5-band graphic equaliser a 5-band graphic equaliser is provided, which can be applied to the adc or dac path , together with 3d enhancement, under control of the eq3dmode register bit. the adcs and dacs should be disabled before changing the aq3dmode bit. register address bit label default description r18 eq control 1 8 eq3dmode 1 0 = equaliser and 3d enhancement applied to adc path 1 = equaliser and 3d enhancement applied to dac path table 23 eq and 3d enhancement dac or adc path select the equaliser consists of low and high frequency shelving filters (band 1 and 5) and three peak filters for the centre bands. each has adjustable cut-off or centre frequency, and selectable boost (+/- 12db in 1db steps). the peak filters have selectable bandwidth. register address bit label default description 4:0 eq1g 01100 (0db) band 1 gain control. see table 29 for details. r18 eq band 1 control 6:5 eq1c 01 band 1 cut-off frequency: 00 = 80hz 01 = 105hz 10 = 135hz 11 = 175hz table 24 eq band 1 control register address bit label default description 4:0 eq2g 01100 (0db) band 2 gain control. see table 29 for details. 6:5 eq2c 01 band 2 centre frequency: 00 = 230hz 01 = 300hz 10 = 385hz 11 = 500hz r19 eq band 2 control 8 eq2bw 0 band 2 bandwidth control 0 = narrow bandwidth 1 = wide bandwidth table 25 eq band 2 control register address bit label default description 4:0 eq3g 01100 (0db) band 3 gain control. see table 29 for details. 6:5 eq3c 01 band 3 centre frequency: 00 = 650hz 01 = 850hz 10 = 1.1khz 11 = 1.4khz r20 eq band 3 control 8 eq3bw 0 band 3 bandwidth control 0 = narrow bandwidth 1 = wide bandwidth table 26 eq band 3 control
wm8983 product preview w pp rev 1.1 august 2005 44 register address bit label default description 4:0 eq4g 01100 (0db) band 4 gain control. see table 29 for details 6:5 eq4c 01 band 4 centre frequency: 00 = 1.8khz 01 = 2.4khz 10 = 3.2khz 11 = 4.1khz r21 eq band 4 control 8 eq4bw 0 band 4 bandwidth control 0 = narrow bandwidth 1 = wide bandwidth table 27 eq band 4 control register address bit label default description 4:0 eq5g 01100 (0db) band 5 gain control. see table 29 for details. r22 eq band 5 gain control 6:5 eq5c 01 band 5 cut-off frequency: 00 = 5.3khz 01 = 6.9khz 10 = 9khz 11 = 11.7khz table 28 eq band 5 control gain register gain 00000 +12db 00001 +11db 00010 +10db 00011 +9db 00100 +8db 00101 +7db 00110 +6db 00111 +5db 01000 +4db 01001 +3db 01010 +2db 01011 +1db 01100 0db 01101 -1db 11000 -12db 11001 to 11111 reserved table 29 gain register table see also figure 51 to figure 68 for equaliser and high pass filter responses.
product preview wm8983 w pp rev 1.1 august 2005 45 3d stereo enhancement the wm8983 has a digital 3d enhancement option to increase the perceived separation between the left and right channels. selection of 3d for record or playback is controlled by register bit eq3dmode. switching this bit from record to playback or from playback to record may only be done when adc and dac are disabled. the wm8983 control interface will only allow eq3dmode to be changed when adc and dac are disabled (ie adcenl = 0, adcenr = 0, dacenl = 0 and dacenr = 0). the depth3d setting controls the degree of stereo expansion. when 3d enhancement is used, it may be necessary to attenuate the signal by 6db to avoid limiting. register address bit label default description r41 (29h) 3d control 3:0 depth3d[3:0] 0000 stereo depth 0000: 0% (minimum 3d effect) 0001: 6.67% 0010: 13.33 0011: 20.00 0100: 26.67 0101: 33.33 0110: 40.0 0111: 46.67 1000: 53.33 1001: 60.00 1010: 66.67 1011: 73.33 1100: 80.00 1101: 86.67 1110: 93.3% 1111: 100% (maximum 3d effect) table 30 3d stereo enhancement function analogue outputs the wm8983 has three sets of stereo analogue outputs. these are: ? lout1 and rout1 which are normally used to drive a headphone load. ? lout2 and rout2 C which can be used as speaker, headphone or line drivers. ? out3 and out4 C can be configured as a stereo line out (out3 is left output and out4 is right output). out4 can also be used to provide a mono mix of left and right channels. the outputs lout2, rout2 out3 and out4 are powered from avdd2 and are capable of driving a 1v rms signal (avdd1/3.3) in non-boost mode and avdd1*1.5/3.3 in boost mode. lout1 and rout1 are supplied from avdd1 and can drive out a 1v rms signal (avdd1/3.3). lout1, rout1, lout2 and rout2 have individual analogue volume pgas with -57db to +6db gain ranges. there are four output mixers in the output signal path , the left and right channel mixers which control the signals to headphone (and optionally the line outputs) and also dedicated out3 and out4 mixers.
wm8983 product preview w pp rev 1.1 august 2005 46 left and right output channel mixers the left and right output channel mixers are shown in figure 23. these mixers allow the aux inputs, the adc bypass and the dac left and right channels to be combined as desired. this allows a mono mix of the dac channels to be performed as well as mixing in external line-in from the aux or speech from the input bypass path. the aux and bypass inputs have individual volume control from -15db to +6db and the dac volume can be adjusted in the digital domain if required. the output of these mixers is connected to the headphone outputs (lout1, rout1, lout2 and rout2) and can optionally be connected to the out3 and out4 mixers. figure 23 left/right output channel mixers
product preview wm8983 w pp rev 1.1 august 2005 47 register address bit label default description r43 output mixer control 8 bypl2rmix 0 left bypass path (from the left channel input pga stage) to right output mixer 0 = not selected 1 = selected r43 output mixer control 7 bypr2lmix 0 right bypass path (from the right channel input pga stage) to left output mixer 0 = not selected 1 = selected 5 dacr2lmix 0 right dac output to left output mixer 0 = not selected 1 = selected r49 output mixer control 6 dacl2rmix 0 left dac output to right output mixer 0 = not selected 1 = selected 0 dacl2lmix 1 left dac output to left output mixer 0 = not selected 1 = selected 1 bypl2lmix 0 left bypass path (from the left channel input pga stage) to left output mixer 0 = not selected 1 = selected 4:2 byplmixvol 000 left bypass volume contol to output channel mixer: 000 = -15db 001 = -12db 010 = -9db 011 = -6db 100 = -3db 101 = 0db 110 = +3db 111 = +6db 5 auxl2lmix 0 left auxilliary input to left channel output mixer: 0 = not selected 1 = selected r50 left channel output mixer control 8:6 auxlmixvol 000 aux left channel input to left mixer volume control: 000 = -15db 001 = -12db 010 = -9db 011 = -6db 100 = -3db 101 = 0db 110 = +3db 111 = +6db
wm8983 product preview w pp rev 1.1 august 2005 48 0 dacr2rmix 1 right dac output to right output mixer 0 = not selected 1 = selected 1 bypr2rmix 0 right bypass path (from the right channel input pga stage) to right output mixer 0 = not selected 1 = selected 4:2 byprmixvol 000 right bypass volume control to output channel mixer: 000 = -15db 001 = -12db 010 = -9db 011 = -6db 100 = -3db 101 = 0db 110 = +3db 111 = +6db 5 auxr2rmix 0 right auxiliary input to right channel output mixer: 0 = not selected 1 = selected r51 right channel output mixer control 8:6 auxrmixvol 000 aux right channel input to right mixer volume control: 000 = -15db 001 = -12db 010 = -9db 011 = -6db 100 = -3db 101 = 0db 110 = +3db 111 = +6db 2 lmixen 0 left output channel mixer enable: 0 = disabled 1 = enabled r3 power management 3 3 rmixen 0 right output channel mixer enable: 0 = disabled 1 = enabled table 31 left and right output mixer control
product preview wm8983 w pp rev 1.1 august 2005 49 headphone outputs (lout1 and rout1) the headphone outputs lout1 and rout1 can drive a 16 ? or 32 ? headphone load, either through dc blocking capacitors, or dc-coupled to a buffered midrail reference as shown in figure 24. out3, out4, lout2 or rout2 could be used as this buffered reference if one of these outputs is not being used, saving decoupling capacitors, at the expense of increased power consumption. for fully independent left and right channels, two separate midrail references can be used, eliminating crosstalk caused by headphone ground impedances, at the expense of increased power consumption. headphone output using dc blocking capacitors: lowest power consumption (two outputs enabled); large and expensive capacitors; bass response may be reduced for smaller capacitors; impedance in common ground may introduce crosstalk. dc coupled headphone output: higher power consumption (three outputs enabled); improved psrr if avdd2 connected to avdd1; impedance in common ground may introduce crosstalk; improved bass response (dc connection). dc coupled with fully independent left / right drive: highest power consumption (four outputs enabled); improved psrr if avdd2 connected to avdd1; independent l/r pseudo-ground eliminates crosstalk; improved bass response (dc connection); non-standard headphone connection may not be suitable for some applications. figure 24 recommended headphone output configurations each headphone output has an analogue volume control pga with a gain range of -57db to +6db. when dc blocking capacitors are used, their capacitance and the load resistance together determine the lower cut-off frequency of the output signal, f c . increasing the capacitance lowers f c , improving the bass response. smaller capacitance values will diminish the bass response. assuming a 16 ? load and c1, c2 = 220 f: f c = 1 / 2 r l c 1 = 1 / (2 x 16 ? x 220 f) = 45 hz in the dc coupled configuration, the headphone ground is connected to the vmid pin. the out3/4 pins can be configured as a dc output driver by setting the out3mute and out4mute register bit. the dc voltage on vmid in this configuration is equal to the dc offset on the lout1 and rout1 pins therefore no dc blocking capacitors are required. this saves space and material cost in portable applications. note that lout2, rout2, out3 and out4 have an optional output boost of 1.5x. when these are configured in this output boost mode ( spkboost/out3boost/out4boost=1) t hen the vmid value of these outputs will be equal to 1.5xavdd/2 and will not match the vmid of the headphone drivers. do not use the dc coupled output mode in this configuration. it is recommended to connect the dc coupled outputs only to headphones, and not to the line input of another device. although the built-in short circuit protection will prevent any damage to the headphone outputs, such a connection may be noisy, and may not function properly if the other device is grounded.
wm8983 product preview w pp rev 1.1 august 2005 50 register address bit label default description 7 lout1zc 0 headphone volume zero cross enable: 1 = change gain on zero cross only 0 = change gain immediately 6 lout1mute 0 left headphone output mute: 0 = normal operation 1 = mute 5:0 lout1vol 111001 left headphone output volume: 000000 = -57db 000001 = -56db ... 111001 = 0db ... 111111 = +6db r52 lout1 volume control 8 hpvu not latched lout1 and rout1 volumes do not update until a 1 is written to out1vu (in reg 52 or 53) 7 rout1zc 0 headphone volume zero cross enable: 1 = change gain on zero cross only 0 = change gain immediately 6 rout1mute 0 right headphone output mute: 0 = normal operation 1 = mute 5:0 rout1vol 111001 right headphone output volume: 000000 = -57db 000001 = -56db 111001 = 0db ... 111111 = +6db r53 rout1 volume control 8 hpvu not latched lout1 and rout1 volumes do not update until a 1 is written to out1vu (in reg 52 or 53) table 32 out1 volume control speaker outputs (lout2 and rout2) the outputs lout2 and rout2 are designed to drive an 8 ? btl speaker but can optionally drive two headphone loads of 16 ? /32 ? or a line output (see headphone output and line output sections, respectively). each output has an individual volume control pga, an output boost/level shift bit, a mute and an enable as shown in figure 25. lout2 and rout2 output the left and right channel mixer outputs respectively. the rout2 signal path also has an optional invert. the amplifier used for this invert can be used to mix in the auxr signal with an adjustable gain range of -15db -> +6db. this allows a beep signal to be applied only to the speaker output without affecting the hp or line outputs.
product preview wm8983 w pp rev 1.1 august 2005 51 figure 25 speaker outputs lout2 and rout2
wm8983 product preview w pp rev 1.1 august 2005 52 speaker boost mode to support speaker boost mode, avdd2 should be at least 1.5*avdd1. a higher avdd2 will improve thd performance at the expense of power consumption while lower avdd2 will cause clipping. variations in avdd1 and avdd2 should be taken into account when using speaker boost mode as shown in figure 26 and figure 27. figure 26 non-boost mode output operation figure 27 boost mode output operation lout2 and rout2 outputs can be connected directly to a lithium battery to improve thd performance in non-boost mode. although direct battery connection is also possible in boost mode, the discharge characteristic of the battery can lead to clipping after a relatively short period of time as shown in figure 28. reducing the maximum permitted volume and keeping avdd1 to a minimum will allow boost mode to operate for longer. figure 28 output boost mode with direct battery connection as the full scale output falls close to avdd1, it becomes more effective to use non-boost mode to generate a louder output, although s pkboost s hould not be changed while the speaker output is driving out a signal. as a general rule: if avdd2 - (avdd1 * 0.75) > avdd1 / 2 boost mode provides more power output; if avdd2 - (avdd1 * 0.75) < avdd1 / 2 non-boost mode provides more power output.
product preview wm8983 w pp rev 1.1 august 2005 53 register address bit label default description 7 lout2zc 0 lout2 volume zero cross enable: 1 = change gain on zero cross only 0 = change gain immediately 6 lout2mute 0 left output mute: 0 = normal operation 1 = mute 5:0 lout2vol 111001 left output volume: 000000 = -57db 000001 = -56db ... 111001 = 0db ... 111111 = +6db r54 lout2 volume control 8 spkvu not latched lout2 and rout2 volumes do not update until a 1 is written to out2vu (in reg 54 or 55) 7 rout2zc 0 rout2 volume zero cross enable: 1 = change gain on zero cross only 0 = change gain immediately 6 rout2mute 0 right output mute: 0 = normal operation 1 = mute 5:0 rout2vol 111001 right output volume: 000000 = -57db 000001 = -56db ... 111001 = 0db ... 111111 = +6db r55 rout2 volume control 8 spkvu not latched lout2 and rout2 volumes do not update until a 1 is written to out2vu (in reg 54 or 55) table 33 out2 volume control the signal output on lout2/rout2 comes from the left/right mixer circuits and can be any combination of the dac output, the bypass path (output of the input boost stage) and the aux input. the lout2/rout2 volume is controlled by the lout2vol/ rout2vol register bits. gains over 0db may cause clipping if the signal is large. the lout2mute/ rout2mute register bits cause the speaker outputs to be muted (the output dc level is driven out). the output pins remain at the same dc level (dcop), so that no click noise is produced when muting or un-muting the speaker output stages also have a selectable gain boost of 1.5x (3.52db). when this boost is enabled the output dc level is also level shifted (from avdd1/2 to 1.5xavdd1/2) to prevent the signal from clipping. a dedicated amplifier bufdcop, as shown in figure 29, is used to perform the dc level shift operation. this buffer must be enabled using the bufdcopen register bit for this operating mode. it should also be noted that if avdd2 is not equal to or greater than 1.5xavdd1 this boost mode may result in signals clipping. table 35 summarises the effect of the spkboost control bits.
wm8983 product preview w pp rev 1.1 august 2005 54 register address bit label default description r49 output control 2 spkboost 0 0 = s peaker gain = -1; dc = avdd1 / 2 1 = speaker gain = +1.5; dc = 1.5 x avdd1 / 2 r1 power management 1 8 bufdcopen 0 dedicated buffer for dc level shifting output stages when in 1.5x gain boost configuration. 0 = buffer disabled 1 = buffer enabled (required for 1.5x gain boost) table 34 speaker boost stage control spkboost output stage gain output dc level output stage configuration 0 1x (0db) avdd1/2 inverting 1 1.5x (3.52db) 1.5xavdd1/2 non-inverting table 35 output boost stage details register address bit label default description 5 muterpga2inv 0 mute input to invrout2 mixer 4 invrout2 0 invert rout2 output 3:1 beepvol 000 auxr input to rout2 inverter gain 000 = -15db 001 = -12db 010 = -9db 011 = -6db 100 = -3db 101 = 0db 110 = +3db 111 = +6db r43 beep control 0 beepen 0 0 = mute auxr beep input 1 = enable auxr beep input table 36 auxr C rout2 beep mixer function zero cross timeout a zero-cross timeout function is provided so that if zero cross is enabled on the input or output pgas the gain will automatically update after a timeout period if a zero cross has not occurred. this is enabled by setting slowclken. the timeout period is dependent on the clock input to the digital and is equal to 2 21 * sysclk period. register address bit label default description r7 additional control 0 slowclken 0 slow clock enable. used for both the jack insert detect debounce circuit and the zero cross timeout. 0 = slow clock disabled 1 = slow clock enabled table 37 timeout clock enable control
product preview wm8983 w pp rev 1.1 august 2005 55 out3/out4 mixers and output stages the out3/out4 pins provide an additional stereo line output, a mono output, or a pseudo ground connection for headphones. there is a dedicated analogue mixer for out3 and one for out4 as shown in figure 30. the out3 and out4 output stages are powered from avdd2 and agnd2. these individually- controllable outputs also incorporate an optional 1.5x boost and level shifting stage. figure 30 out3 and out4 mixers out3 can provide a midrail reference, a left line output, or a mono mix line output out4 can provide a midrail reference, a right line output, or a mono mix line output. a 6db attenuation function is provided for out4, to prevent clipping during mixing of left and right signals. this function is enabled by the out4attn register bit.
wm8983 product preview w pp rev 1.1 august 2005 56 register address bit label default description 6 out3mute 0 0 = output stage outputs out3 mixer 1 = output stage muted C drives out vmid. can be used as vmid reference in this mode. 3 out4_2out3 0 out4 mixer output to out3 0 = disabled 1 = enabled 2 bypl2out3 0 left adc input to out3 0 = disabled 1 = enabled 1 lmix2out3 0 left dac mixer to out3 0 = disabled 1= enabled r56 out3 mixer control 0 ldac2out3 1 left dac output to out3 0 = disabled 1 = enabled 7 out3_2out4 0 out3 mixer output to out4 0 = disabled 1= enabled 6 out4mute 0 0 = output stage outputs out4 mixer 1 = output stage muted C drives out vmid. can be used as vmid reference in this mode. 5 out4attn 0 0 = out4 normal output 1 = out4 attenuated by 6db 4 lmix2out4 0 left dac mixer to out4 0 = disabled 1 = enabled 3 ldac2out4 0 left dac to out4 0 = disabled 1 = enabled 2 bypr2out4 0 right adc i nput to out4 0 = disabled 1 = enabled 1 rmix2out4 0 right dac mixer to out4 0 = disabled 1 = enabled r57 out4 mixer control 0 rdac2out4 1 right dac output to out4 0 = disabled 1 = enabled table 38 out3/out4 mixer registers the out3 and out4 output stages each have a selectable gain boost of 1.5x (3.52db). when this boost is enabled the output dc level is also level shifted (from avdd1/2 to 1.5xavdd1/2) to prevent the signal from clipping. a dedicated amplifier bufdcop, as shown in figure 31, is used to perform the dc level shift operation. this buffer must be enabled using the bufdcopen register bit for this operating mode. it should also be noted that if avdd2 is not equal to or greater than 1.5xavdd1 this boost mode may result in signals clipping. table 35 summarises the effect o f the out3boost and out4boost control bits.
product preview wm8983 w pp rev 1.1 august 2005 57 figure 32 outputs out3 and out4 register address bit label default description 3 out3boost 0 0 = out3 output gain = -1; dc = avdd1 / 2 1 = out3 output gain = +1.5 dc = 1.5 x avdd1 / 2 r49 output control 4 out4boost 0 0 = out4 output gain = -1; dc = avdd1 / 2 1 = out4 output gain = +1.5 dc = 1.5 x avdd1 / 2 r1 power management 1 8 bufdcopen 0 dedicated buffer for dc level shifting output stages when in 1.5x gain boost configuration. 0=buffer disabled 1=buffer enabled (required for 1.5x gain boost) table 39 out3 and out4 boost stages control out3boost/ out4boost output stage gain output dc level output stage configuration 0 1x avdd1/2 inverting 1 1.5x 1.5xavdd1/2 non-inverting table 40 out3 and out4 output boost stage details
wm8983 product preview w pp rev 1.1 august 2005 58 output phasing the relative phases of the analogue outputs will depend upon the following factors: 1. daclpol and dacrpol invert bits: setting these bits to 1 will invert the dac output. 2. mixer configuration: the polarity of the signal will depend upon the route through the mixer path. for example, dacl can be directly input to the out3 mixer, giving a 180 phase shift at the out3 mixer output. however, if dacl is input to the out3 mixer via the left mixer, an additional phase shift will be introduced, giving 0 phase shift at the out3 mixer output. 3. output boost set-up: when 1.5x boost is enabled on an output, no phase shift occurs. when 1.5x boost is not enabled, a 180 phase shift occurs. figure 23 shows where these phase inversions can occur in the output signal path. figure 33 output signal path phasing
product preview wm8983 w pp rev 1.1 august 2005 59 table 41 shows the polarities of the outputs in various configurations. unless otherwise stated, polarity is shown with respect to left dac output in non-inverting mode. note that only registers relating to the mixer paths are shown here (mixer enables, volume settings, output enables etc are not shown). configuration daclpol dacrpol invrout2 spkboost out3boost out4boost mixer path registers different from default out4 phase / mag out3 phase / mag lout1 phase / mag rout1 phase / mag lout2 phase / mag rout2 phase / mag default: stereo dac playback to lout1/rout1, lout2/rout2 and out4/out3 0 0 0 0 0 0 0 1 0 1 0 1 0 1 180 1 180 1 dacs inverted 1 1 0 0 0 0 180 1 180 1 180 1 180 1 0 1 0 1 stereo dac playback to lout1/rout1 and lout2/rout2 and out4/out3 (speaker boost enabled) 0 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1.5 0 1.5 stereo dac playback to lout1/rout1 and lout2/rout2 and out4/out3 (out3 and out4 boost enabled) 0 0 0 0 1 1 180 1.5 180 1.5 0 1 0 1 180 1 180 1 stereo playback to out3/out4 (dacs input to out3/out4 mixers via left/right mixers) 0 0 0 0 0 0 ldac2out3=0 rdac2out4=0 lmix2out3=1 rmix2out4=1 180 1 180 1 0 1 0 1 180 1 180 1 differential output of right bypass path via out3/out4 (phase shown relative to right bypass) 0 0 0 0 0 0 bypr2out4=1 out4_2out3=1 180 1 0 1 x x x x differential output of mono mix of dacs via lout2/rout2 (e.g. btl speaker drive) 0 0 1 0 0 0 0 1 0 1 0 1 0 1 180 1 0 1 high power speaker drive 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1.5 180 1.5 table 41 relative output phases note that differential output should not be set up by combining outputs in boost mode with outputs which are not in boost mode as this would cause a dc offset current on the outputs.
wm8983 product preview w pp rev 1.1 august 2005 60 enabling the outputs each analogue output of the wm8983 can be independently enabled or disabled. the analogue mixer associated with each output has a separate enable bit. all outputs are disabled by default. to save power, unused parts of the wm8983 should remain disabled. outputs can be enabled at any time, but it is not recommended to do so when bufio is disabled (bufioen=0), as this may cause pop noise (see power management and applications information sections). register address bit label default description 2 bufioen 0 unused input/output bias buffer enable 6 out3mixen 0 out3 mixer enable 7 out4mixen 0 out4 mixer enable r1 power management 1 8 bufdcopen 0 output stage 1.5xavdd/2 driver enable 8 rout1en 0 rout1 output enable 7 lout1en 0 lout1 output enable r2 power management 2 6 sleep 0 0 = normal device operation 1 = supply current reduced in device standby mode 2 lmixen 0 left mixer enable 3 rmixen 0 right mixer enable 5 rout2en 0 rout2 output enable 6 lout2en 0 lout2 output enable 7 out3en 0 out3 enable r3 power management 3 8 out4en 0 out4 enable 1 delen 0 2 nd enable bit for l/rout1 r42 output ctrl1 0 out1del 0 2 stage enable for l/rout1 note: all enable bits are 1 = on, 0 = off table 42 output stages power management control out1del and out2del enable lower pop noise power-up option. see startCup sequences. (in 2 stage enable method, normal enable bit is set, followed shortly later by the delayed enable delen) thermal shutdown to protect the wm8983 from overheating a thermal shutdown circuit is included. if the device temperature reaches approximately 125 0 c and the thermal shutdown circuit is enabled (tsden=1) the l/rout2 amplifiers will be disabled. the thermal shutdown may also be configured to generate an interrupt. see the gpio and interrupt controller section for details. register address bit label default description r49 output control 1 tsden 0 thermal shutdown enable 0 : thermal shutdown disabled 1 : thermal shutdown enabled table 43 thermal shutdown
product preview wm8983 w pp rev 1.1 august 2005 61 unused analogue inputs/outputs whenever an analogue input/output is disabled, it remains connected to a voltage source (either avdd1/2 or 1.5xavdd1/2 as appropriate) through a resistor. this helps to prevent pop noise when the output is re-enabled. the resistance between the voltage buffer and the output pins can be controlled using the vroi control bit. the default impedance is low, so that any capacitors on the outputs can charge up quickly at start-up. if a high impedance is desired for disabled outputs, vroi can then be set to 1, increasing the resistance to about 30k ? . register address bit label default description r49 0 vroi 0 vref (avdd1/2 or 1.5xavdd/2) to analogue output resistance 0: approx 1k ? 1: approx 30 k ? table 44 disabled outputs to vref resistance a dedicated buffer is available for biasing unused analogue i/o pins as shown in figure 34. this buffer can be enabled using the bufioen register bit. if the spkboost, out3boost or out4boost bits are set then the relevant outputs will be tied to the output of the dc level shift buffer at 1.5xavdd/2 when disabled. figure 34 summarises the bias options for the output pins. figure 34 unused input/output pin tie-off buffers
wm8983 product preview w pp rev 1.1 august 2005 62 l/rout2en/ out3/4en out3boost/ out4boost/ spkboost vroi output configuration 0 0 0 1k ? tie-off to avdd1/2 0 0 1 30k ? tie-off to avdd1/2 0 1 0 1k ? tie-off to 1.5xavdd1/2 0 1 1 30k ? tie-off to 1.5xavdd1/2 1 0 x output enabled (dc level=avdd1/2) 1 1 x output enabled (dc level=1.5xavdd1/2) table 45 unused output pin bias options digital audio interfaces the audio interface has four pins: ? adcdat: adc data output ? dacdat: dac data input ? lrc: data left/right alignment clock ? bclk: bit clock, for synchronisation the clock signals bclk, and lrc can be outputs when the wm8983 operates as a master, or inputs when it is a slave (see master and slave mode operation, below). five different audio data formats are supported: ? left justified ? right justified ? i 2 s ? dsp mode early ? dsp mode late all of these modes are msb first. they are described in audio data formats, below. refer to the electrical characteristic section for timing information. master and slave mode operation the wm8983 audio interface may be configured as either master or slave. as a master interface device the wm8983 generates bclk and lrc and thus controls sequencing of the data transfer on adcdat and dacdat. to set the device to master mode register bit ms should be set high. in slave mode (ms=0), the wm8983 responds with data to clocks it receives over the digital audio interfaces. audio data formats in left justified mode, the msb is available on the first rising edge of bclk following an lrc transition. the other bits up to the lsb are then transmitted in order. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles before each lrc transition. figure 35 left justified audio interface (assuming n-bit word length)
product preview wm8983 w pp rev 1.1 august 2005 63 in right justified mode, the lsb is available on the last rising edge of bclk before a lrc transition. all other bits are transmitted before (msb first). depending on word length, bclk frequency and sample rate, there may be unused bclk cycles after each lrc transition. figure 36 right justified audio interface (assuming n-bit word length) in i 2 s mode, the msb is available on the second rising edge of bclk following a lrc transition. the other bits up to the lsb are then transmitted in order. depending on word length, bclk frequency and sample rate , there may be unused bclk cycles between the lsb of one sample and the msb of the next. figure 37 i 2 s audio interface (assuming n-bit word length) in dsp/pcm mode, the left channel msb is available on either the 1 st (mode b) or 2 nd (mode a) rising edge of bclk (selectable by lrp) following a rising edge of lrc. right channel data immediately follows left channel data. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles between the lsb of the right channel data and the next sample. in device master mode, the lrc output will resemble the lrc pulse shown in figure 38 and figure 39. in device slave mode, figure 40 and figure 41, it is possible to use any length of lrc pulse less than 1/fs, providing the falling edge of the lrc pulse occurs greater than one bclk period before the rising edge of the next lrc pulse. figure 38 dsp/pcm mode audio interface (mode a, lrp=0, master)
wm8983 product preview w pp rev 1.1 august 2005 64 figure 39 dsp/pcm mode audio interface (mode b, lrp=1, master) figure 40 dsp/pcm mode audio interface (mode a, lrp=0, slave) figure 41 dsp/pcm mode audio interface (mode b, lrp=0, slave)
product preview wm8983 w pp rev 1.1 august 2005 65 register address bit label default description 0 mono 0 selects between stereo and mono device operation: 0 = stereo device operation 1 = mono device operation. data appears in left phase of lrc. 1 adclrswap 0 controls whether adc data appears in right or left phases of lrc clock: 0=adc left data appear in left phase of lrc and right data in 'right' phase 1=adc left data appear in right phase of lrc and right data in 'left' phase 2 daclrswap 0 controls whether dac data appears in right or left phases of lrc clock: 0=dac left data appear in left phase of lrc and right data in 'right' phase 1=dac left data appear in right phase of lrc and right data in 'left' phase 4:3 fmt 10 audio interface data format select: 00=right justified 01=left justified 10=i 2 s format 11= dsp/pcm mode 6:5 wl 10 word length 00=16 bits 01=20 bits 10=24 bits 11=32 bits (see note) 7 lrp 0 lrc clock polarity 0=normal 1=inverted r4 audio interface control 8 bcp 0 bclk polarity 0=normal 1=inverted r5 0 loopback 0 digital loopback function 0=no loopback 1=loopback enabled, adc data output is fed directly into dac data input. table 46 audio interface control note: right justified mode will only operate with a maximum of 24 bits. if 32-bit mode is selected the device will operate in 24-bit mode. audio interface control the register bits controlling audio format, word length and master / slave mode are summarised below. register bit ms selects audio interface operation in master or slave mode. in master mode bclk and lrc are outputs. the frequencies of bclk and lrc in master mode are controlled using mclkdiv; these clocks are divided down versions of pll output clock (sysclk). the mclkdiv default setting provides a sysclk/256 division rate for the lrc output clock. it is possible to divide down the bclk rate using bclkdiv; care must be taken in choosing the correct bclkdiv rate to maintain sufficient bclk pulses per lrc period for the chosen data word length. the bclkdiv default setting provides a bclk = sysclk clock.
wm8983 product preview w pp rev 1.1 august 2005 66 register address bit label default description 0 ms 0 sets the chip to be master over lrc and bclk 0=bclk and lrc clock are inputs (slave mode) 1=bclk and lrc clock are outputs generated by the wm8983 (master mode) 4:2 bclkdiv 000 configures the bclk and lrc output frequency, for use when the chip is in master mode. 000=divide by 1 (bclk=sysclk) 001=divide by 2 (bclk=sysclk/2) 010=divide by 4 011=divide by 8 100=divide by 16 101=divide by 32 110=reserved 111=reserved 7:5 mclkdiv 010 sets the division for either the mclk or pll clock output (selected by clksel) 000=divide by 1 001=divide by 1.5 010=divide by 2 (lrc=sysclk/256) 011=divide by 3 100=divide by 4 101=divide by 6 110=divide by 8 111=divide by 12 r6 clock generation control 8 clksel 1 controls the source of the clock for all internal operation: 0=mclk 1=pll output table 47 clock control sample rate (khz) sysclk (mhz) (256fs clock) mclkdiv r6 [bit 7:5] sr r7 [bit3:1] 8 12.288 111 = divide by 12 010 11.025 11.2896 110 = divide by 8 100 12 12.288 110 = divide by 8 100 16 12.288 101 = divide by 6 011 22.05 11.2896 100 = divide by 4 010 24 12.288 100 = divide by 4 010 32 12.288 011 = divide by 3 001 44.1 11.2896 010 = divide by 2 000 48 12.288 010 = divide by 2 000 table 48 register settings and required sysclk for common sample rates
product preview wm8983 w pp rev 1.1 august 2005 67 loopback setting the loopback register bit enables digital loopback. when this bit is set the output data from the adc audio interface is fed directly into the dac data input. companding the wm8983 supports a-law and -law companding on both transmit (adc) and receive (dac) sides. companding can be enabled on the dac or adc audio interfaces by writing the appropriate value to the dac_comp or adc_comp register bits respectively. register address bit label default description 2:1 adc_comp 0 adc companding 00 = off 01 = reserved 10 = -law 11 = a-law 4:3 dac_comp 0 dac companding 00 = off 01 = reserved 10 = -law 11 = a-law r5 companding control 5 wl8 0 0 = off 1 = device operates in 8-bit mode. table 49 companding control companding involves using a piecewise linear approximation of the following equations (as set out by itu-t g.711 standard) for data compression: -law (where =255 for the u.s. and japan): f(x) = ln( 1 + |x|) / ln( 1 + ) -1 x 1 law (where a=87.6 for europe): f(x) = a|x| / ( 1 + lna) } for x 1/a f(x) = ( 1 + lna|x|) / (1 + lna) } for 1/a x 1 the companded data is also inverted as recommended by the g.711 standard (all 8 bits are inverted for -law, all even data bits are inverted for a-law). the data will be transmitted as the first 8 msbs of data. companding converts 13 bits ( -law) or 12 bits (a-law) to 8 bits using non-linear quantization. the input data range is separated into 8 levels, allowing low amplitude signals better precision than that of high amplitude signals. this is to exploit the operation of the human auditory system, where louder sounds do not require as much resolution as quieter sounds. the companded signal is an 8- bit word containing sign (1-bit), exponent (3-bits) and mantissa (4-bits). setting the wl8 register bit allows the device to operate with 8-bit data . in this m ode it is possible to use 8 bclks per lrc frame. when using dsp mode b, this allows 8-bit data words to be output consecutively every 8 bclks and can be used with 8-bit data words using the a-law and u-law companding functions. bit8 bit[7:4] bit[3:0] sign exponent mantissa table 50 8-bit companded word composition
wm8983 product preview w pp rev 1.1 august 2005 68 u-law companding 0 20 40 60 80 100 120 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 normalised input companded output 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 normalised output figure 42 -law companding a-law companding 0 20 40 60 80 100 120 0 0.2 0.4 0.6 0.8 1 normalised input companded output 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 normalised output figure 43 a-law companding
product preview wm8983 w pp rev 1.1 august 2005 69 audio sample rates the wm8983 filter characteristics for the adcs and the dacs are set using the sr register bits; these bits do not change the rate of the audio interface output clocks in master mode. the cut-offs for the digital filters and the alc attack/decay times stated are determined using these values and assume a 256fs master clock rate. if a sample rate is required which is not explicitly supported by the sr register settings, then the closest sr value to that sample rate should be chosen, the filter characteristics and the alc attack, decay and hold times will scale appropriately. register address bit label default description r7 additional control 3:1 sr 000 approximate sample rate (configures the coefficients for the internal digital filters): 000 = 48khz 001 = 32khz 010 = 24khz 011 = 16khz 100 = 12khz 101 = 8khz 110-111 = reserved table 51 sample rate control master clock and phase locked loop (pll) the wm8983 has an on-chip phase-locked loop (pll) circuit that can be used to: generate master clocks for the wm8983 audio functions from another external clock, e.g. in telecoms applications. generate and output (on pin csb/gpio1) a clock for another part of the system that is derived from an existing audio master clock. figure 44 shows the pll and internal clocking on the wm8983. the pll can be enabled or disabled by the pllen register bit. register address bit label default description r1 power management 1 5 pllen 0 pll enable 0 = pll off 1 = pll on table 52 pllen control bit
wm8983 product preview w pp rev 1.1 august 2005 70 figure 44 pll and clock select circuit the pll frequency ratio r = f 2 /f 1 (see figure 44) can be set using the register bits pllk and plln. r should be chosen to ensure 5 < plln < 13: plln = int r pllk = int (2 24 (r-plln)) to calculate r : there is a fixed divide by 4 in the pll, f/4, and a selectable divide by n after the pll, mclkdiv. ? f 2 = sysclk x 4 x mclkdiv ? r = f 2 / (mclk / prescale) = r ? plln = int r ? k = int ( 2 24 x (r C intr)) C convert k to hex for pllk example: mclk=26mhz, required clock = 12.288mhz. r should be chosen to ensure 5 < plln < 13. mclkdiv = 2 sets the required division rate; sysclk/ 256. ? f 2 = 4 x 2 x 12.288mhz = 98.304mhz. ? r = 98.304 / (26/2) = 7.561846 ? plln = int r = 7 ? k = int ( 2 24 x (7.561846 C 7)) = 9426214 dec convert k to hex: pllk = 8fd526h convert pllk to r36, r37, r38 and r39 hex values: r36 = 7h; r37 = 23h; r38 = 1eah; r39 = 126h
product preview wm8983 w pp rev 1.1 august 2005 71 register address bit label default description 4 pllprescale 0 divide mclk by 2 before input to pll r36 pll n value 3:0 plln 1000 integer (n) part of pll input/output frequency ratio. use values greater than 5 and less than 13. r37 pll k value 1 5:0 pllk [23:18] 0ch r38 pll k value 2 8:0 pllk [17:9] 093h r39 pll k value 3 8:0 pllk [8:0] 0e9h fractional (k) part of pll1 input/output frequency ratio (treat as one 24-digit binary number). table 53 pll frequency ratio control the pll performs best when f 2 is around 90mhz. its stability peaks at n=8. some example settings are shown in table 54. mclk (mhz) (f1) desired output (mhz) f2 (mhz) prescale divide mclkdiv r plln r36 (hex) k (hex) pllk [23:18] r37 (hex) pllk [17:9] r38 (hex) pllk [8:0] r39 (hex) 12 11.29 90.3168 1 2 7.5264 7 86c226 21 161 26 12 12.288 98.304 1 2 8.192 8 3126e8 c 93 e9 13 11.29 90.3168 1 2 6.947446 6 f28bd4 3c 145 1d4 13 12.288 98.304 1 2 7.561846 7 8fd525 23 1ea 126 14.4 11.29 90.3168 1 2 6.272 6 45a1ca 11 d0 1ca 14.4 12.288 98.304 1 2 6.826667 6 d3a06e 34 1d0 6d 19.2 11.29 90.3168 2 2 9.408 9 6872af 1a 39 b0 19.2 12.288 98.304 2 2 10.24 a 3d70a3 f b8 a3 19.68 11.29 90.3168 2 2 9.178537 9 2db492 b da 92 19.68 12.288 98.304 2 2 9.990243 9 fd809f 3f c0 9f 19.8 11.29 90.3168 2 2 9.122909 9 1f76f7 7 1bb f8 19.8 12.288 98.304 2 2 9.929697 9 ee009e 3b 100 9e 24 11.29 90.3168 2 2 7.5264 7 86c226 21 161 26 24 12.288 98.304 2 2 8.192 8 3126e8 c 93 e9 26 11.29 90.3168 2 2 6.947446 6 f28bd4 3c 145 1d4 26 12.288 98.304 2 2 7.561846 7 8fd525 23 1ea 126 27 11.29 90.3168 2 2 6.690133 6 boac93 2c 56 94 27 12.288 98.304 2 2 7.281778 7 482296 12 11 96 table 54 pll frequency examples for common mclk rates
wm8983 product preview w pp rev 1.1 august 2005 72 general purpose input/output the wm8983 has three dual purpose input/output pins. ? csb/gpio1: csb / gpio1 pin ? l2/gpio2: left channel line input / headphone detection input ? r2/gpio3: right channel line input / headphone detection input the gpio2 and gpio3 functions are provided for use as jack detection inputs. the gpio1 and gpio2 functions are provided for use as jack detection inputs or general purpose outputs. the default configuration for the csb/gpio1 is to be an input. when setup as an input, the csb/gpio1 pin can either be used as csb or for jack detection, depending on how the mode pin is set. table 55 illustrates the functionality of the gpio1 pin when used as a general purpose output. register address bit label default description 2:0 gpio1sel 000 csb/gpio1 pin function select: 000= input (csb/jack detection: depending on mode setting) 001 = reserved 010 = temp ok 011 = amute active 100 = pll clk output 101 = pll lock 110 = logic 0 111 = logic 1 3 gpio1pol 0 gpio1 polarity invert 0 = non inverted 1 = inverted r8 gpio control 5:4 opclkdiv 00 pll output clock division ratio 00 = divide by 1 01 = divide by 2 10 = divide by 3 11 = divide by 4 table 55 csb/gpio control note: if mode is set to 3 wire mode, csb/gpio1 is used as csb input irrespective of the gpio1sel[2:0] bits. for further details of the jack detect operation see the output switching section. output switching (jack detect) when the device is operated using a 2-wire interface the csb/gpio1 pin can be used as a switch control input to automatically disable one set of outputs and enable another. the l2/gpio2 and r2/gpio3 pins can also be used for this purpose. the gpio pins have an internal de-bounce circuit when in this mode in order to prevent the output enables from toggling multiple times due to input glitches. this de-bounce circuit is clocked from a slow clock with period 2 21 x mclk. note that the gpiopol bit is not relevant for jack detection, it is the si gnal detected at the pin which is used. the switching on/off of the outputs is fully configurable by the user. each output, out1, out2, out3 and out4 has 2 associated enables. out1_en_0, out2_en_0, out3_en_0 and out4_en_0 are the output enable signals which are used if the selected jack detection pin is at logic 0 (after de-bounce). out1_en_1, out2_en_1, out3_en_1 and out4_en_1 are the output enable signals which are used if the selected jack detection pin is at logic 1 (after de-bounce).
product preview wm8983 w pp rev 1.1 august 2005 73 similar to the output enables, vmid can be output to out3. this vmid output can be configured to be on/off depending on the jack detection input polarity of vmid_en_0 and vmid_en_1. the jack detection enables operate as follows: all out_en signals have an and function performed with their normal enable signals (in table 42). when an output is normally enabled at per table 42, the selected jack detection enable (controlled by selected jack detection pin polarity) is set 0, it will turn the output off. if the normal enable signal is already off (0), the jack detection signal will have no effect due to the and function. during jack detection if the user desires an output to be un-changed whether the jack is in or not, both the jd_en settings i.e. jd_en0 and jd_en1, should be set to 0000. the vmid_en signal has an or function performed with the normal vmid driver enable. if the vmid_en signal is to have no effec t to normal functi onality when jack detection is enabled, it should set to 0 for all jd_en0 or jd_en1 settings. if jack detection is not enabled (jd_en=0), the output enables default to all 1s, allowing the outputs to be controlled as normal via the normal output enables found in table 42. similarly the vmid_en signal defaults to 0 allowing the vmid driver to be controlled via the normal enable bit. register address bit label default description 5:4 jd_sel 00 pin selected as jack detection input 00 = gpio1 01 = gpio2 10 = gpio3 11 = reserved 6 jd_en 0 jack detection enable 0 = disabled 1 = enabled r9 gpio control 8:7 jd_vmid 00 [7] vmid_en_0 [8] vmid_en_1 3:0 jd_en0 0000 output enables when selected jack detection input is logic 0. 0000 = out1_en_0 0001 = out2_en_0 0010 = out3_en_0 0011 = out4_en_0 0100-1111 = reserved r13 7:4 jd_en1 0000 output enables when selected jack detection input is logic 1 0000-0011 = reserved 0100 = out1_en_1 0101 = out2_en_1 0110 = out3_en_1 0111 = out4_en_1 1000-1111 = reserved table 56 jack detect register control bits
wm8983 product preview w pp rev 1.1 august 2005 74 control interface selection of control mode and 2-wire mode address the control interface can operate as either a 3-wire or 2-wire control interface. the mode pin determines the 2 or 3 wire mode as shown in table 57. the wm8983 is controlled by writing to registers through a serial control interface. a control word consists of 16 bits. the first 7 bits (b15 to b9) are register address bits that select which control register is accessed. the remaining 9 bits (b8 to b0) are data bits, corresponding to the 9 data bits in each control register. mode interface format low 2 wire high 3 wire table 57 control interface mode selection 3-wire serial control mode in 3-wire mode, every rising edge of sclk clocks in one data bit from the sdin pin. a rising edge on csb/gpio latches in a complete control word consisting of the last 16 bits. figure 45 3-wire serial control interface 2-wire serial control mode the wm8983 supports software control via a 2-wire serial bus. many devices can be controlled by the same bus, and each device has a unique 7-bit device address (this is not the same as the 7-bit address of each register in the wm8983). the wm8983 operates as a slave device only. the controller indicates the start of data transfer with a high to low transition on sdin while sclk remains high. this indicates that a device address and data will follow. all devices on the 2-wire bus respond to the start condition and shift in the next eight bits on sdin (7-bit address + read/write bit, msb first). if the device address received matches the address of the wm8983, the wm8983 responds by pulling sdin low on the next clock pulse (ack). if the address is not recognised or the r/w bit is 1 when operating in write only mode, the wm8983 returns to the idle condition and waits for a new start condition and valid address. during a write, once the wm8983 has acknowledged a correct address , the controller sends the first byte of control data (b15 to b8, i.e. the wm8983 register address plus the first bit of register data). the wm8983 then acknowledges the first data byte by driving sdin low for one clock cycle. the controller then sends the second byte of control data (b7 to b0, i.e. the remaining 8 bits of register data), and the wm8983 acknowledges again by pulling sdin low. transfer is complete when there is a low to high transition on sdin while sclk is high. after a complete sequence the wm8983 returns to the idle state and waits for another start condition. if a start or stop condition is detected out of sequence at any point during data transfer (i.e. sdin changes while sclk is high), the control interface returns to the idle condition. sdin sclk register address and 1st register data bit device address (7 bits) rd / wr bit ack (low) control byte 1 (bits 15 to 8) control byte 1 (bits 7 to 0) remaining 8 bits of register data stop start ack (low) ack (low) figure 46 2-wire serial control interface
product preview wm8983 w pp rev 1.1 august 2005 75 in 2-wire mode the wm8983 has a fixed device address, 0011010. resetting the chip the wm8983 can be reset by performing a write of any value to the software reset register (address 0h). this will cause all register values to be reset to their default values. in addition to this there is a power-on reset (por) circuit which ensures that the registers are initially set to default when the device is powered up. power supplies the wm8983 requires four separate power supplies: avdd1 and agnd1: analogue supply, powers all internal analogue functions and output drivers lout1 and rout1. avdd1 must be between 2.5v and 3.6v and has the most significant impact on overall power consumption (except for power consumed in the headphones). higher avdd1 will improve audio quality. avdd2 and agnd2: output driver supplies, power lout2, rout2, out3 and out4. avdd2 must be between 2.5v and 5.5v. avdd2 can be tied to avdd1, but it requires separate layout and decoupling capacitors to curb harmonic distortion. dcvdd: digital core supply, powers all digital functions except the audio and control interfaces. dcvdd must be between 1.71v and 3.6v, and has no effect on audio quality. the return path for dcvdd is dgnd, which is shared with dbvdd. dbvdd must be between 1.71v and 3.6v. dbvdd return path is through dgnd. it is possible to use the same supply voltage for all four supplies. however, digital and analogue supplies should be routed and decoupled separately on the pcb to keep digital switching noise out of the analogue signal paths. power management saving power by reducing oversampling rate the default mode of operation of the adc and dac digital filters is in 64x oversampling mode. under the control of adcosr128 and dacosr128 the oversampling rate may be doubled. 64x oversampling results in a slight decrease in noise performance compared to 128x but lowers the power consumption of the device. register address bit label default description r10 dac control 3 dacosr128 0 dac oversample rate select 0 = 64x (lowest power) 1 = 128x (best snr) r14 adc control 3 adcosr128 0 adc oversample rate select 0 = 64x (lowest power) 1 = 128x (best snr) table 58 adc and dac oversampling rate selection vmid the analogue cicruitry will not operate unless vmid is enabled. the impedance of the vmid resistor string, together with the decoupling capacitor on the vmid pin will determine the startup time of the vmid circuit. register address bit label default description r1 power management 1 1:0 vmidsel 00 reference string impedance to vmid pin (determines startup time): 00 = off (250k ? vmid to agnd1) 01 = 100k ? total, 25k ? impedance 10 = 500k ? total, 125k ? impedance 11 = 10k ? total, 2.5k ? impedance table 59 vmid impedance control
wm8983 product preview w pp rev 1.1 august 2005 76 biasen the analogue amplifiers will not operate unless bi asen is enabled. register address bit label default description r1 power management 1 3 biasen 0 analogue amplifier bias control 0 = disabled 1 = enabled table 60 analogue bias control bias control control of the analog bias values is possible using register 61 and 62 register address bit label default description 8 biascut 0 global bias control 0 = normal 1 = 0.5x 6 half_ ipga 0 input bias control 0 = normal 1 = 0.5x 4,3 bufbias 01 adc input buffer bias 00 = 1.5x 01 = 1.0x 10 = 1.0x 11 = 0.5x 2,1 adcbias 01 adc input buffer bias 00 = 1.5x 01 = 1.0x 10 = 1.0x 11 = 0.5x r61 bias control 0 halfop bias 0 output bias 0 = normal 1 = 0.5x r62 3 half daci 0 dac bias 0 = normal 1 = 0.5x table 61 analogue bias control note that these bits must be used with care and may cause degradation in analog performance. for example, if both biascut and halfdaci are used at same time, the playback thd will be poor.
product preview wm8983 w pp rev 1.1 august 2005 77 register map addr b[15:9] deft val d e c h e x register name b8 b7 b6 b5 b4 b3 b2 b1 b0 (hex) 0 00 software reset software reset 1 01 power manage?t 1 bufdc open out4 mixen out3 mixen pllen micben biasen bufio en vmidsel 000 2 02 power manage?t 2 rout1 en lout1 en sleep boost enr boost enl inpga enr inppga enl adc enr adc enl 000 3 03 power manage?t 3 out4en out3en lout2 en rout2 en 0 rmixen lmixen dac enr dac enl 000 4 04 audio interface bcp lrp wl fmt dlr swap alr swap mono 050 5 05 companding ctrl 0 0 0 wl8 dac_comp adc_comp loop back 000 6 06 clock gen ctrl clksel mclkdiv bclkdiv 0 ms 140 7 07 additional ctrl 0 0 0 0 0 sr slowc lk en 000 8 08 gpio stuff 0 0 0 opclkdiv gpio1p ol gpio1sel[2:0] 000 9 09 jack detect control jd_vmid 1 jd_vmi d0 jd_en jd_sel 0 0 0 0 000 10 0a dac control 0 0 soft mute 0 0 dac osr128 amute dacr pol dacl pol 000 11 0b left dac digital vol dacvu daclvol 0ff 12 0c right dac dig?l vol dacvu dacrvol 0ff 13 0d jack detect control 0 jd_en1 jd_en0 000 14 0e adc control hpfen hpfapp hpfcut adc osr128 0 adcr pol adc lpol 100 15 0f left adc digital vol adcvu adclvol 0ff 16 10 right adc digital vol adcvu adcrvol 0ff 18 12 eq1 ? low shelf eq3d mode 0 eq1c eq1g 12c 19 13 eq2 ? peak 1 eq2bw 0 eq2c eq2g 02c 20 14 eq3 ? peak 2 eq3bw 0 eq3c eq3g 02c 21 15 eq4 ? peak 3 eq4bw 0 eq4c eq4g 02c 22 16 eq5 ? high shelf 0 0 eq5c eq5g 02c 24 18 dac limiter 1 limen limdcy limatk 032 25 19 dac limiter 2 0 0 limlvl limboost 000 27 1b notch filter 1 nfu nfen nfa0[13:7] 000 28 1c notch filter 2 nfu 0 nfa0[6:0] 000 29 1d notch filter 3 nfu 0 nfa1[13:7] 000 30 1e notch filter 4 nfu 0 nfa1[6:0] 000 32 20 alc control 1 alcsel 0 alcmax alcmin 038 33 21 alc control 2 alczc alchld alclvl 00b 34 22 alc control 3 alc mode alcdcy alcatk 032
wm8983 product preview w pp rev 1.1 august 2005 78 addr b[15:9] deft val d e c h e x register name b8 b7 b6 b5 b4 b3 b2 b1 b0 (hex) 35 23 noise gate 0 0 0 0 0 ngen ngth 000 36 24 pll n 0 0 0 0 pllpre scale plln[3:0] 008 37 25 pll k 1 0 0 0 pllk[23:18] 00c 38 26 pll k 2 pllk[17:9] 093 39 27 pll k 3 pllk[8:0] 0e9 41 29 3d control depth3d 000 42 2a out4 to adc out4_2adcvol out4_2 lnr 0 0 pob ctrl delen out1 del 43 2b beep control bypl2 rmix bypr2 lmix 0 0 0 0 0 0 0 000 44 2c input ctrl micbv sel 0 r2_2 inppga rin2 inppga rip2 inppga 0 l2_2 inppga lin2 inppga lip2 inppga 003 45 2d left inp pga gain ctrl inpgavu inppga zcl inppga mutel inppgavoll 010 46 2e right inp pga gain ctrl inpgavu inppga zcr inppga muter inppgavolr 010 47 2f left adc boost ctrl pga boostl 0 l2_2boostvol 0 auxl2boostvol 100 48 30 right adc boost ctrl pga boostr 0 r2_2boostvol 0 auxr2boostvol 100 49 31 output ctrl 0 0 dacl2 rmix dacr2 lmix out4 boost out3 boost spk boost tsden vroi 002 50 32 left mixer ctrl auxlmixvol auxl2 lmix byplmixvol bypl2 lmix dacl2 lmix 001 51 33 right mixer ctrl auxrmixvol auxr2 rmix byprmixvol bypr2 rmix dacr2 rmix 001 52 34 lout1 (hp) volume ctrl out1vu lout1 zc lout1 mute lout1vol 039 53 35 rout1 (hp) volume ctrl out1vu rout1 zc rout1 mute rout1vol 039 54 36 lout2 (spk) volume ctrl out2vu lout2 zc lout2 mute lout2vol 039 55 37 rout2 (spk) volume ctrl out2vu rout2 zc rout2 mute rout2vol 039 56 38 out3 mixer ctrl 0 0 out3 mute 0 0 out4_ 2out3 bypl2 out3 lmix2 out3 ldac2 out3 001 57 39 out4 (mono) mixer ctrl 0 out3_2 out4 out4 mute out4 attn lmix2 out4 ldac2 out4 bypr2 out4 rmix2 out4 rdac2 out4 001 61 3d bias control biascut 0 half i_ipga 0 bufbias[1:0] adcbias[1:0] half opbias 000 table 62 wm8983 register map
product preview wm8983 w pp rev 1.1 august 2005 79 digital filter characteristics parameter test conditions min typ max unit adc filter +/- 0.025db 0 0.454fs passband -6db 0.5fs passband ripple +/- 0.025 db stopband 0.546fs stopband attenuation f > 0.546fs -60 db group delay 21/fs adc high pass filter -3db 3.7 -0.5db 10.4 high pass filter corner frequency -0.1db 21.6 hz dac filter +/- 0.035db 0 0.454fs passband -6db 0.5fs passband ripple +/-0.035 db stopband 0.546fs stopband attenuation f > 0.546fs -80 db group delay 29/fs table 63 digital filter characteristics terminology 1. stop band attenuation (db) C the degree to which the frequency spectrum is attenuated (outside audio band) 2. pass-band ripple C any variation of the frequency response in the pass-band region
wm8983 product preview w pp rev 1.1 august 2005 80 dac filter responses -120 -100 -80 -60 -40 -20 0 00.511.522.53 frequency (fs) response (db) -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0 0.1 0.2 0.3 0.4 0.5 frequency (fs) response (db) figure 47 dac digital filter frequency response figure 48 dac digital filter ripple adc filter responses -120 -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 frequency (fs) response (db) -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0 0.1 0.2 0.3 0.4 0.5 frequency (fs) response (db) figure 49 adc digital filter frequency response figure 50 adc digital filter ripple
product preview wm8983 w pp rev 1.1 august 2005 81 highpass filter the wm8983 has a selectable digital highpass filter in the adc filter path. this filter has two modes, audio and applications. in audio mode the filter is a 1 st order iir with a cut-off of around 3.7hz. in applications mode the filter is a 2 nd order high pass filter with a selectable cut-off frequency. -40 -35 -30 -25 -20 -15 -10 -5 0 5 0 5 10 15 20 25 30 35 40 45 frequency (hz) response (db) figure 51 adc highpass filter response, hpfapp=0 -60 -50 -40 -30 -20 -10 0 10 0 200 400 600 800 1000 1200 frequency (hz) response (db) -80 -70 -60 -50 -40 -30 -20 -10 0 10 0 200 400 600 800 1000 1200 frequency (hz) response (db) figure 52 adc highpass filter responses (48khz), hpfapp=1, all cut-off settings shown. figure 53 adc highpass filter responses (24khz), hpfapp=1, all cut-off settings shown. -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 0 200 400 600 800 1000 1200 frequency (hz) response (db) figure 54 adc highpass filter responses (12khz), hpfapp=1, all cut-off settings shown.
wm8983 product preview w pp rev 1.1 august 2005 82 5-band equaliser the wm8983 has a 5-band equaliser which can be applied to either the adc path or the dac path. the plots from figure 55 to figure 68 show the frequency responses of each filter with a sampling frequency of 48khz, firstly showing the different cut-off/centre frequencies with a gain of 12db, and secondly a sweep of the gain from -12db to +12db for the lowest cut-off/centre frequency of each filter. 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) figure 55 eq band 1 low frequency shelf filter cut-offs figure 56 eq band 1 gains for lowest cut-off frequency 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) figure 57 eq band 2 C peak filter centre frequencies, eq2bw=0 figure 58 eq band 2 C peak filter gains for lowest cut-off frequency, eq2bw=0 10 -2 10 -1 10 0 10 1 10 2 10 3 10 4 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) figure 59 eq band 2 C eq2bw=0, eq2bw=1
product preview wm8983 w pp rev 1.1 august 2005 83 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) figure 60 eq band 3 C peak filter centre frequencies, eq3bw=0 figure 61 eq band 3 C peak filter gains for lowest cut-off frequency, eq3bw=0 10 -2 10 -1 10 0 10 1 10 2 10 3 10 4 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) figure 62 eq band 3 C eq3bw=0, eq3bw=1
wm8983 product preview w pp rev 1.1 august 2005 84 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) figure 63 eq band 4 C peak filter centre frequencies, eq3bw=0 figure 64 eq band 4 C peak filter gains for lowest cut-off frequency, eq4bw=0 10 -2 10 -1 10 0 10 1 10 2 10 3 10 4 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) figure 65 eq band 4 C eq3bw=0, eq3bw=1 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) figure 66 eq band 5 high frequency shelf filter cut-offs figure 67 eq band 5 gains for lowest cut-off frequency
product preview wm8983 w pp rev 1.1 august 2005 85 figure 68 shows the result of having the gain set on more than one channel simultaneously. the blue traces show each band (lowest cut-off/centre frequency) with 12db gain. the red traces show the cumulative effect of all bands with +12db gain and all bands -12db gain, with eqxbw=0 for the peak filters. 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -15 -10 -5 0 5 10 15 20 frequency (hz) magnitude (db) figure 68 cumulative frequency boost/cut
wm8983 product preview w pp rev 1.1 august 2005 86 applications information recommended external components figure 69 external component diagram
product preview wm8983 w pp rev 1.1 august 2005 87 package diagram dm030.e fl: 32 pin qfn plastic package 5 x 5 x 0.9 mm body, 0.50 mm lead pitch notes: 1. dimension b applied to metallized terminal and is measured between 0.25 mm and 0.30 mm from terminal tip. dimension l1 repr esents terminal pull back from package side wall. maximum of 0.1mm is acceptable. where terminal pull back exists, only u pper half of lead is visible on package side wall due to half etching of leadframe. 2. falls within jedec, mo-220 with the exception of d2, e2: d2,e2: larger pad size chosen which is just outside jedec specification 3. all dimensions are in millimetres 4. this drawing is subject to change without notice. 5. shape and size of corner tie bar may vary with package terminal count. corner tie bar is connected to exposed pad internall y. 6. refer to application note wan_0118 for further information regarding pcb footprints and qfn package soldering. see detail b e2 e2/2 b b 16 15 a 8 9 e 5 corner tie bar b d2 l d2/2 see detail a index area (d/2 x e/2) top view d c aaa 2 x c aaa 2 x e detail b terminal tip r datum e e/2 l1 1 detail a b c bbb m a 32x b l 32x k l1 r 1 1 0 . 5 6 6 m m 0 . 4 3 m m 5 corner tie bar symbols dimensions (mm) min nom max note a a1 a3 b d d2 e e2 e l l1 r 0.85 0.90 1.00 0.05 0.02 0 0.2 ref 0.30 0.23 0.18 5.00 3.4 3.3 3.2 0.5 bsc 0.35 0.4 0.45 0.1 b(min)/2 1 2 2 1 k 0.20 aaa bbb ccc ref: 0.15 0.10 0.10 jedec, mo-220, variation vhhd-2 tolerances of form and position 4.90 5.10 5.00 4.90 5.10 3.4 3.3 3.2 1 17 24 25 32 exposed ground paddle 6 exposed ground paddle bottom view c 0.08 c ccc a a1 c (a3) seating plane 1 side view
wm8983 product preview w pp rev 1.1 august 2005 88 important notice wolfson microelectronics plc (wm) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. all products are sold subject to the wm terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. wm warrants performance of its products to the specifications applicable at the time of sale in accordance with wms standard warranty. testing and other quality control techniques are utilised to the extent wm deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. in order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards. wolfson products are not authorised for use as critical components in life support devices or systems without the express written approval of an officer of the company. life support devices or systems are devices or systems that are intended for surgical implant into the body, or support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be reasonably expected to result in a significant injury to the user. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. wm assumes no liability for applications assistance or customer product design. wm does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of wm covering or relating to any combination, machine, or process in which such products or services might be or are used. wms publication of information regarding any third partys products or services does not constitute wms approval, license, warranty or endorsement thereof. reproduction of information from the wm web site or datasheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. representation or reproduction of this information with alteration voids all warranties provided for an associated wm product or service, is an unfair and deceptive business practice, and wm is not responsible nor liable for any such use. resale of wms products or services with statements different from or beyond the parameters stated by wm for that product or service voids all express and any implied warranties for the associated wm product or service, is an unfair and deceptive business practice, and wm is not responsible nor liable for any such use. address: wolfson microelectronics plc westfield house 26 westfield road edinburgh eh11 2qb united kingdom tel :: +44 (0)131 272 7000 fax :: +44 (0)131 272 7001 email :: sales@wolfsonmicro.com

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